Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-02-07
2004-12-21
Beausoliel, Robert (Department: 2122)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C717S126000, C714S001000, C714S004110
Reexamination Certificate
active
06834357
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of operating an embedded system and to an embedded system, also to a method and apparatus for data communication between a host computer and a target computer system and more particularly but not exclusively between a host computer and an embedded target computer system.
BACKGROUND OF THE INVENTION
During development and testing of an embedded computer system, especially an embedded microprocessor-based computer system, it is normally necessary to connect the system to a host computer so that an engineer can debug the embedded system. Debugging software on the host computer provides access by the engineer into the embedded system. Typically, the engineer uses the host computer and debugging software to set break points which stop threads of execution on the target embedded system, monitor registers in the target, monitor memory states and monitor input and output data. The engineer may also restart threads that have been previously stopped and perform a variety of other tasks including rebooting the target computer using the host.
Although in normal operation the embedded system may be virtually self-sufficient in that it does not in normal use need to perform input/output, it may be necessary during debugging for such input/output to be performed. Examples of this are displaying messages at the host, reading characters from the host keyboard or reading data from a file stored on the host.
Similar situations requiring input/output may occur where an embedded system is sold to an end user and the end user needs to customize the embedded system, for example writing information into programmable read only memory in the embedded system.
Embedded systems may contain more than one application, for instance stored in a read only memory or downloaded over a link, at run-time. An example of the latter is a satellite transmission link. Each such application may need to perform input output of data to the host computer during debugging. Furthermore, applications may be interconnected so that one application that is executing may, at a virtually arbitrary point in time, cause another application to start executing. Although it is possible to provide input/output libraries during the construction of each application, such libraries, and as a result the protocol implemented by the application for input/output, may differ between applications.
As a result, debug tools on the host may have difficulties in communicating with target applications which have different versions of input/output libraries, and it may be impossible for communication to occur. Typically, applications built with input/output libraries which differ in vintage from the debug tools resident on the host will not be able to perform input/output with the host; this may result in the target “hanging”, waiting for an input from the host in response to a message from the target, which message has not been recognised by the host.
The Open System Interconnect (OSI) seven-layer model provides a commonly-used guideline for developing standards for communication interchange. The model envisages seven layers for controlling communication ranging from the deepest level, the application layer at level 7 through the data link layer at level 2 and the physical layer at level 1. Generally speaking, use of the OSI model envisages that information will have an additional header added to it upon each transition from a deeper level to the next less-deep level until the information is provided on the physical link. Then, upon reception, the headers will be successively removed until the information is again at the application level. Where the data-link layer (level 2) of the host-target communication protocol is implemented by the reading from and writing to of volatile memory in the address space of the target—the target lacking specific hardware to implement the input output protocol at this level—the problem identified above is further compounded.
Typically, each application may be built individually, with a linker dynamically determining the addressable locations used for protocol implementation. If there is more than one application needing to perform input/output, the host will not be able to determine easily which memory locations should be used at a particular point in time. It would of course be possible to arrange a system which reserved locations in memory for protocol use but this requires application developer intervention regarding the input/output implementation.
As used herein, the term ‘digital signal processor’ includes microprocessors in general and other like digitally operating processing devices.
It is accordingly a primary object of the present invention to at least partially overcome the difficulties of the prior art.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention there is provided a method of operating an embedded system comprising a digital signal processor and associated memory, said embedded system having an application program for running on said digital signal processor and a link external to said embedded system, said link being capable of connection to a host computer, said memory comprising a pointer location for storing pointer information representative of the location of the entry point of a computer file comprising a communication subroutine, the method comprising: running said application program, whereby said application program identifies a need for communication over said link; establishing the contents of said pointer location to determine whether said pointer location contents represent a valid address in said memory; if said contents of said pointer location are established as representing a valid address in said memory, calling said valid address; determining whether code at said valid address indicates a said entry point, thereby determining whether a said computer file is present; if said computer file is present, running said subroutine to thereby communicate.
According to a second aspect of the present invention there is provided a method of data communication between a host computer and a target computer system, wherein said target computer system has a memory comprising plural addressable locations and is adapted to run an application, the method comprising: providing a file comprising a subroutine enabling said communication between said computers; dynamically loading said file from said host computer to said memory of said target computer system whereby said file has an entry point at a dynamically-determined addressable location; storing at a predetermined one of said addressable locations data representative of the address of said entry point; running said application, whereby said application determines said data representative of said address thereby accessing said subroutine; and running said subroutine whereby said communication occurs.
According to a third aspect of the present invention there is provided an embedded system comprising a digital signal processor and associated memory, said embedded system having an application program for running on said digital signal processor and further having a link external to said embedded system, said link being capable of connection to a host computer, said memory comprising a pointer location for storing pointer information representative of the location of the entry point of a computer file comprising a communication subroutine, the system comprising:
processor circuitry for running said application program, whereby said application program identifies a need for communication over said link;
establishing circuitry for establishing the contents of said pointer location to determine whether said pointer location contents represent a valid address in said memory;
calling circuitry for calling said valid address;
determining circuitry for determining whether code at said valid address indicates a said entry point, whereby said processor circuitry runs said subroutine.
According to a further aspect of the present invention there is provided a device f
Beausoliel Robert
Jorgenson Lisa K.
McCarthy Christopher S.
Morris James H.
STMicroelectronics Limited
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