ESD resistant device

Details ESD resistant device ESD resistant device

2000-05-31

2002-12-03

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S238000, C438S275000, C438S294000

Reexamination Certificate

active

06489232

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection, and, more particularly, for a fabricated device such as a photodetector having increased resistance to ESD.
2. Description of the Related Art
A wide variety of devices are fabricated using semiconductor substrates. These devices include integrated circuits (ICs) and other fabricated semiconductor devices such as photodetectors. Photodetectors include APD (avalanche photodiode) and PIN photodetectors, which convert light received into a signal current. The acronym PIN (p-i-n) stands for P-type-Intrinsic type-N-type, i.e. the initials of the three layers that make up the classic diode. A PIN diode is a p-n junction with a doping profile tailored in such a way that an intrinsic layer, “i region,” is sandwiched in between a p layer and an n layer. InP-based PIN photodetectors, for example, are widely used as a component in optical communication systems.
Such semiconductor devices are vulnerable to damage from electrostatic discharge (ESD). ESD damage to the device active region of a photodetector can result from discharge of charge stored on the device surface for example.
Referring now to
FIG. 1
, there is shown a cross-sectional view of a portion of a conventional device
100
with surface charge Q that may result in ESD damage to device
100
. Device
100
is, for example, an APD or PIN photodetector, fabricated as a chip from a wafer substrate such as InP. Photodetector
100
has N contacts
107
and P contact
101
for applying a bias voltage and for receiving a current signal proportional to the light incident on the bottom layer, between N contacts
107
, via a lens (not shown). Substrate layer
104
is an n-type InP material layer. Dielectric layer
103
is, for example, a fully-passivating nitride layer. Layer
106
is an n-type region, composed, for example, of InGaAs, and other layers (not shown). Device
100
has a chip thickness H.
The active region
110
of device
100
contains P metal contact
101
, and the general active region beneath P contact
101
, including P-type diffused junction region
105
. P contact
101
is epitaxially grown cap layer, composed of p-contact metal. Junction
105
is a circular diffused P-type junction within N-type layer
106
, and to which the metal of P contact
101
is applied. The term “dot” is sometimes employed to refer to these devices, since the junction is typically less than 100 &mgr;m in diameter and the chip is typically more than 500 &mgr;m across. The area of the junction, roughly equivalent to the area of the P contact
101
, is sometimes referred to as the “p-dot”. P contact
101
is sometimes referred to as the detector dot contact.
In both PIN and APD discrete devices the active region
110
of the device
100
typically comprises a small fraction of the semiconductor used to create the device. Surface charge Q, which is proportional to the area of the chip, can discharge through the P contact
101
and thus through the device active area
110
, i.e. into P contact
101
, and through diffused junction
105
and surrounding layers
106
, thus damaging the device. ESD can damage the device, for example, at the region of highest electric field, at the junction of the absorption region (of layer
106
) with the P region of diffused junction
105
. In an APD, this is the multiplication region and is closely adjacent to the heterojunction.
ESD due to discharge of surface charge on the side of the device containing the device active region can therefore cause premature failure of devices such as communication photodetectors, thus posing a significant reliability threat to the operation and manufacture of such devices. Photodetectors used in laser package and other lightwave subassemblies, for example, can be very susceptible to ESD damage. This is because PIN and APD photodetectors which are used for signal applications are characterized by having very small junction areas (to get low capacitance for high speed) surrounded by relatively large chips (for handling and bonding). This leads to a high current density through the device active region, when there is an ESD caused by discharge of surface charge on the active region surface of the device. Further discussion of ESD and its effect on devices such as photodetectors may be found in H. Neitzert and A. Piccirillo, “Sensitivity of multimode bidirectional optoelectronic modules to electrostatic discharges,”
Microelectronics Reliability
39(1999): 1863-1871; T. Diep, S. Phatak, D. Yoo, “PIN Photodetectors—the ESD bottleneck in Laser Packages,”
Proc. EOS/ESD Symposium
92 (1992): 159; S. Voldman, “The State of the Art of Electrostatic Discharge Protection: Physics, Technology, Circuits, Design, Simulation and Scaling,”
IEEE Journal of Solid-State Circuits
34 (1999): 1272-1282.
One approach to minimizing ESD damage from discharge of surface charge is to enlarge the area of the device active region to minimize the current density of the discharge. However, this increases the capacitance of the device, thereby decreasing bandwidth performance.
SUMMARY
A semiconductor device such as a photodetector has a substrate having an active region layer containing an active region of the device. A dielectric layer is disposed on the active region layer, and a metal active region contact is disposed in the dielectric layer above the active region and electrically contacting the active region. A metal electrostatic discharge (ESD) protection structure is disposed in the dielectric layer around the active region contact, wherein the ESD protection structure electrically contacts the active region layer of the substrate to provide an ESD discharge path for charge on the surface of the dielectric layer.


REFERENCES:
patent: 4821089 (1989-04-01), Strauss
patent: 6121080 (2000-09-01), Wu

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