ESD protection that supports LVDS and OCT

Details ESD protection that supports LVDS and OCT ESD protection that supports LVDS and OCT

2007-07-31

2007-07-31

Soward, Ida M. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S173000, C257S174000, C257S356000, C257S357000, C257S358000, C257S359000, C257S360000, C257S361000, C257S362000, C257S363000

Reexamination Certificate

active

10891988

ABSTRACT:
Circuits are described that provide electrostatic discharge protection for I/O circuits that support the low voltage differential signaling (LVDS) and on-chip termination (OCT) standards. At least one additional transistor is connected across an I/O transistor. In the case of LVDS, a pair of stacked transistors is used in which the distance between the source/drain region and a well tap is considerably greater for the transistor connected to the I/O pad. A PMOS transistor and an NMOS transistor may also be connected in series between a first node such as a power supply node and the I/O pad. An OCT circuit is also disclosed in which the spacing between the source/drain region and a well tap in the OCT transistor is smaller than that in the I/O transistor.

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patent: 2006/0202711 (2006-09-01), Kubo

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