ESD protection system for an integrated circuit with multiple po

Details ESD protection system for an integrated circuit with multiple po ESD protection system for an integrated circuit with multiple po

1996-09-30

1998-04-14

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, H02H 900

Patent

active

057400008

ABSTRACT:
An ESD protection system for protecting a CMOS integrated circuit (IC) with multiple power supplies is provided. The ESD protection system uses on-chip diodes to route ESD current from a first IC pin to the main positive power supply, where it is partly absorbed by the parasitic capacitance between the positive supply and ground. A charge sharing diode is provided between the main power supply and the clean power supply networks so that more of the ESD current may be absorbed by the parasitic capacitance between the clean power supply networks and ground. A core shunt circuit, which turns on when an ESD event is sensed, is provided to directly shunt ESD current from the positive supply to ground. Another diode is used to route current from the ground network out a second IC pin.

REFERENCES:
patent: 5287241 (1994-02-01), Puar
patent: 5430595 (1995-07-01), Wagner et al.
patent: 5485024 (1996-01-01), Reay
patent: 5515225 (1996-05-01), Gens et al.
patent: 5530612 (1996-06-01), Maloney
"ESD Design Methodology", Richard Merril, Enayet Issaq. National Semiconductor Fairchild Research Center, 2900 Semiconductor Drive, Santa Clara, CA 95051; From: EOS/ESD Symposium 93-233; pp. 5B.5.1-5B.5.5 (5 pages).

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