ESD protection snapback structure for overvoltage...

Details ESD protection snapback structure for overvoltage... ESD protection snapback structure for overvoltage...

2005-10-04

2005-10-04

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S336000, C257S337000, C257S349000, C257S412000, C257S343000

Reexamination Certificate

active

06952039

ABSTRACT:
In a self protection I/O, a multiple gate NMOS structure is designed to shift the avalanche multiplication region away from the edge of the gate nearest the drain. This is achieved by providing a lightly doped region between the edge of the gate and the ballast region of the drain.

REFERENCES:
patent: 6004849 (1999-12-01), Gardner et al.
patent: 6229182 (2001-05-01), Van Lieverloo
patent: 6323074 (2001-11-01), Jiang et al.
patent: 6365937 (2002-04-01), Porter et al.
patent: 6465768 (2002-10-01), Ker et al.
patent: 6514839 (2003-02-01), Ker et al.
patent: 6521952 (2003-02-01), Ker et al.
patent: 6661060 (2003-12-01), Lee et al.
patent: 2001/0012666 (2001-08-01), Hsu
patent: 2002/0055233 (2002-05-01), Mitros
patent: 2002/0145165 (2002-10-01), Yang

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