ESD protection power clamp for suppressing ESD events...

Details ESD protection power clamp for suppressing ESD events... ESD protection power clamp for suppressing ESD events...

2006-08-01

2006-08-01

Sircus, Brian (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

07085113

ABSTRACT:
An ESD protection power clamp for suppressing ESD events. A clamping transistor having power source connections connected across the power supply terminals of an integrated circuit is connected to clamp the voltage during an ESD event. An RC timing circuit defines a time interval where ESD voltage for triggering the FET out of conduction. An inverter circuit connects the RC and timing circuit to the clamping FET. A dynamic feedback transistor is connected in series with one stage of the inverter and the power supply. During an ESD event, the feedback transistor delays the time for disabling the FET transistor, providing increased immunity against mistriggering of the clamping transistor, and forces the circuit to reset following the mistrigger event.

REFERENCES:
patent: 5559659 (1996-09-01), Strauss
patent: 6369994 (2002-04-01), Voldman
patent: 6552886 (2003-04-01), Wu et al.

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