Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-24
2002-11-26
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S350000
Reexamination Certificate
active
06486515
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming an electrostatic discharge device using silicon-on-insulator (SOI) technology in the fabrication of integrated circuits.
(2) Description of the Prior Art
Electrostatic discharge (ESD) refers to a high voltage accidentally applied to an integrated circuit. ESD can result from either automated or human handling. If the voltage applied to the gate insulator becomes excessive, the gate oxide can break down. MOSFET devices are particularly vulnerable to ESD damage. Because of this danger, ESD protection transistors are fabricated to direct ESD current away from the circuit it is protecting.
An isolation technology that depends on completely surrounding devices by an insulator is referred to as silicon-on-insulator (SOI) technology. In general, the advantages of SOI technology include simple fabrication sequence, reduced capacitive coupling between circuit elements, and increased packing density. The SOI technology is discussed in
Silicon Processing for the VLSI Era
, Vol. 2, by S. Wolf, Lattice Press, Sunset Beach, Calif., c. 1990, pp. 66-67.
The present invention makes an electrostatic discharge (ESD) device using silicon-on-insulator (SOI) technology. SOI technology presents challenges to ESD protection because the presence of the insulator layer (oxide) sandwiched between the two silicon layers prevents the discharge of charges. This may lead to more severe ESD.
A number of patents present a variety of methods to form ESD devices. Co-pending U.S. patent application Ser. No. 09/434,922 (CS-99-156) to the same inventors, filed on Nov. 5, 1999, teaches forming an ESD device within a trench using shallow trench isolation technology. Co-pending U.S. patent application Ser. No. 09/531,786 (CS-99-275) to the same inventors, filed on Mar. 21, 2000, discloses an ESD device using SOI technology. U.S. Pat. No. 5,923,067 to Voldman discloses a three-dimensional CMOS-on-SOI ESD device. U.S. Pat. No. 5,856,214 to Yu shows an ESD device having wells and diodes. U.S. Pat. No. 5,674,761 to Chang et al discloses a P/N diode ESD device. U.S. Pat. No. 5,629,544 to Voldman et al shows an ESD SOI device with trench isolations.
SUMMARY OF THE INVENTION
Accordingly, the primary object of the invention is to provide a process for forming an electrostatic discharge device in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming an electrostatic discharge device using silicon-on-insulator technology.
Another object of the invention is to provide a process for forming an electrostatic discharge device using silicon-on-insulator technology and having large area diodes under the oxide.
In accordance with the objects of the invention, a method for forming an electrostatic discharge device using silicon-on-insulator technology is achieved. An N-well is formed within a silicon semiconductor substrate. A P+ region is implanted within a portion of the N-well and an N+ region is implanted within a portion of the semiconductor substrate not occupied by the N-well. An oxide layer is formed overlying the semiconductor substrate. The oxide layer is patterned to form openings to the semiconductor substrate. An epitaxial silicon layer is grown within the openings and overlying the oxide layer. Shallow trench isolation regions are formed within the epitaxial silicon layer extending to the underlying oxide layer. Gate electrodes and associated source and drain regions are formed in and on the epitaxial silicon layer between the shallow trench isolation regions. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. The interlevel dielectric layer is covered with a mask that covers the first contact openings. Second contact openings are opened through the interlevel dielectric layer, shallow trench isolations, and the oxide layer to the N+ region and P+ region. The mask is removed. The first and second contact openings are filled with a conducting layer to complete formation of an electrostatic discharge device in the fabrication of integrated circuits.
REFERENCES:
patent: 5629544 (1997-05-01), Voldman et al.
patent: 5674761 (1997-10-01), Chang et al.
patent: 5856214 (1999-01-01), Yu
patent: 5923067 (1999-07-01), Voldman
patent: 6121661 (2000-09-01), Assaderaghi et al.
patent: 6281530 (2001-08-01), Johnson
patent: 6320232 (2001-11-01), Gossner et al.
patent: 6376881 (2002-04-01), Nagaya
Wolf, “Silicon Processing for the VLSI Era”, vol. 2: Process Integration, Lattice Press, Sunset Beach, Ca, c. 1990, pp. 66-67.
Ang Ting Cheong
Jun Song
Loong Sang Yee
Quek Shyue Fong
Chartered Semiconductor Manufacturing Ltd
Ngo Ngan V.
Pike Rosemary L. S.
Saile George O.
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