ESD protection devices with SCR structures for semiconductor...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S361000, C257S371000

Reexamination Certificate

active

11250508

ABSTRACT:
To control the uneven distribution of current density and reduce the area of an ESD protection circuit in an SCR-type ESD protection device. An N-type well11, and P-type wells12aand12bdisposed oppositely and adjacent to the N-type well11, with the N-type well11interposed between them, are formed on the surface of a semiconductor substrate. A high concentration N-type region15ais formed on the surface of the P-type well12a, a high concentration N-type region15bis formed on the surface of the P-type well12b, and each of them is grounded. Further, a high concentration P-type region14ais formed, oppositely to the high concentration N-type region15a, on the surface of the N-type well11, and a high concentration P-type region14bis formed, oppositely to the high concentration N-type region15b, on the surface of the N-type well11, and each of them is connected to an I/O pad. A high concentration N-type region13is formed on the N-type well11, being interposed between the high concentration P-type region14aand the high concentration P-type region14b, and connected to a trigger device. A surge loaded on the I/O pad is released to the ground terminal via the SCR structures on the both sides.

REFERENCES:
patent: 5270565 (1993-12-01), Lee et al.
patent: 5895940 (1999-04-01), Kim
patent: 6545321 (2003-04-01), Morishita
patent: 6621133 (2003-09-01), Chen et al.
patent: 2004/0136127 (2004-07-01), Kodama et al.
patent: 2003-203985 (2003-07-01), None

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