ESD protection devices and methods for reducing trigger voltage

Details ESD protection devices and methods for reducing trigger voltage ESD protection devices and methods for reducing trigger voltage

2006-03-07

2006-03-07

Baumeister, B. William (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S275000

Reexamination Certificate

active

07009252

ABSTRACT:
ESD protection devices and methods to form them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process, ESD protection devices with a lower trigger voltage are provided. The NMOS for ESD protection according to the present invention has islands with thin gate oxides and a control gate with a thick gate oxide. These islands overlap the drain region of the NMOS to reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

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