ESD protection device with island-like distributed p+...

Details ESD protection device with island-like distributed p+... ESD protection device with island-like distributed p+...

2000-11-29

2003-03-25

Lebentritt, Michael S. (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S349000, C257S350000, C257S351000, C257S357000, C257S360000

Reexamination Certificate

active

06538288

ABSTRACT:

FIELD OF INVENTION
The invention relates to an ESD protection device employing the SCR.
BACKGROUND OF THE INVENTION
In a Human-Body-Model ESD transient, an 100PF capacitor is first charged up to an ESD zapping voltage, and then discharges through a 1.5 Kohms resistor onto an IC pin. For instance, a zapping voltage level of 2 KV is used to qualify an IC package. The initial peak current is roughly 1.2 A with a rise time of approximately 10 nsec. For integrated circuit packages, the VDD-to-VSS capacitance is typically larger than 1 nF. If the ESD energy is directly absorbed by the power bus, i.e. for ESD stress of VDD pin to VSS pin, or indirectly absorbed by the power bus, i.e. the positive ESD stress on an input or I/O pin that has a pull up device, then the voltage-rising rate inside an IC may reach 1 to 2 volt per nano-second for a Human-Body-Model ESD zapping at 2 to 3 KV level. The pull up device includes p+
well diode or PMOSFET.
Transistors, such as grounded-gate NMOS(GGNMOS), field-oxide MOSFET, output buffer transistors, or bipolar transistors, have been commonly used as primary ESD protection elements for integrated circuits. A Semiconductor Controlled Rectifier (SCR), typically including pnpn junctions, can also be used as primary ESD protection device for protecting an IC pin or a power bus during an ESD event. “ESD in Silicon Integrated Circuits” by A. Amerasekera and C. Duvvury, Chap. 3 and 4, John Wiley & Sons, 1995, provides a basic introduction for an SCR used as an ESD protection device.
The conventional SCR is triggered by the nwell to p-substrate junction breakdown, which is relatively high, for instance, typically >20V. This is a drawback when an SCR is used as an ESD protection element since it may not trigger sooner enough during an ESD event to protect other circuit elements from ESD damages.
U.S. Pat. No. 5,465,189 describes an SCR used to provide on-chip protection against ESD stress applied at the input, output, power-supply bus, or between any arbitrary pair of pins of an integrated circuit. A novel structure in the patent having a low breakdown voltage is incorporated into the SCR to lower the trigger voltage of the SCR.
FIG. 1
shows the low-voltage trigger SCR, according to U.S. Pat. No. 5,465,189, which integrates an NMOSFET with the SCR, such that the trigger voltage of the SCR is equal to the trigger voltage of an NMOSFET, which is typically roughly at or lower than 12 volts. As a positive ESD current is applied to the pad or VDD bus, the electrons in the P-substrate
10
flow from n
3
+ region
20
to n
2
+ region
18
. Due to impact ionization, the corresponding holes generated flow into the n
3
+ region
20
and then into the Cathode(GND). The generated holes in the P-substrate
10
renders a voltage drop between substrate and n
3
+ region
20
and therefore a forward-biased condition between P-substrate
10
and n
3
+ region
20
. This condition allows an easier triggering of the SCR formed by the p
1
+/Nwell/P-substrate

3
+. Although the SCR turns on easily with this approach, however, it is possible that, under normal circuit operation without any ESD event, minor substrate current may turn on the SCR unexpectedly. This is the drawback with the approach of FIG.
1
.
FIG. 2
shows a variation of
FIG. 1
in which a P
2
+ region
22
is provided and connected to the Cathode(GND) to overcome the drawback of that in FIG.
1
. As a positive ESD current is applied to the pad or VDD bus, the electrons in the substrate flow from n
3
+ region
20
to n
2
+ region
18
. Due to impact ionization, the corresponding holes generated flow into n
3
+ region
20
and the P
2
+ region
22
, and then into the Cathode(GND). The generated holes in the P-substrate
10
renders a voltage drop between P-substrate
10
and n
3
+ region
20
and therefore a forward-biased condition between P-substrate
10
and n
3
+ region
20
. This condition allows an easier triggering of the SCR formed by the p
1
+/Nwell/P-substrate

3
+. It is noted, due to the existence of the P
2
+ region
22
, some amount of generated holes are absorbed into the GND. Although this approach solve the drawback of that shown in
FIG. 1
, however, the current Itr for triggering the SCR is still a little bit higher than expected.
To overcome the drawbacks mentioned above, the present invention provides an improvement ESD structure.
SUMMARY OF INVENTION
An electrostatic discharge (ESD) protection structure for an integrated circuit constructed on a substrate of a first type is provided.
The protection structure includes a semiconductor controlled rectifier, an MOS transistor and a plurality of island-like distributed diffusion regions of the first type.
The semiconductor controlled rectifier (SCR) is constructed on the base region and coupled to the integrated circuit. The SCR includes a first region of a second type formed next to said base region, a second region of the first type formed in the first region, and a third region of the second type formed in the base region.
The MOS transistor has a drain coupled to the bonding pad and a gate and a source both coupled to a reference ground.
The plurality of island-like distributed diffusion regions of the first type are formed in the base region and each is coupled to the reference ground.


REFERENCES:
patent: 4989057 (1991-01-01), Lu
patent: 5486716 (1996-01-01), Saito et al.
patent: 5923067 (1999-07-01), Voldman
patent: 6034397 (2000-03-01), Voldman

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