ESD protection device having reduced trigger voltage

Details ESD protection device having reduced trigger voltage ESD protection device having reduced trigger voltage

2005-04-19

2005-04-19

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S314000, C257S317000, C257S363000, C257S360000, C257S532000, C257S368000, C257S315000, C257S522000

Reexamination Certificate

active

06882011

ABSTRACT:
An ESD protection device having reduced trigger voltage is disclosed. A first MOS transistor includes a first gate, a first heavily doped region at one side of the first gate, and a second heavily doped region at the other side of the first gate. A second MOS transistor is laterally disposed in proximity to the first MOS transistor. The second MOS transistor includes a second gate, a third heavily doped region at one side of the second gate, and a fourth heavily doped region at the other side of the second gate. The floating gate MOS transistor is located between the first and second MOS transistors. A floating gate MOS transistor is serially connected to the first MOS transistor via the second heavily doped region and is serially connected to the second MOS transistor via the third heavily doped region.

REFERENCES:
patent: 5844300 (1998-12-01), Alavi et al.
patent: 6809386 (2004-10-01), Chaine et al.
patent: 20020195648 (2002-12-01), Hirata

Affiliated with

Also associated with

Rating

ESD protection device having reduced trigger voltage does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with ESD protection device having reduced trigger voltage, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ESD protection device having reduced trigger voltage will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3408346