Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-02-02
2004-11-09
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000, C257S357000, C257S360000, C257S362000
Reexamination Certificate
active
06815775
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed generally to electrostatic discharge (ESD) protection circuits for input/output (I/O) devices, and more particularly, to improving ESD robustness in I/O cell libraries using novel layout techniques to implement a turn-on retraining arrangement that reduces the turn-on speed or increases the breakdown voltage of a MOS transistor.
2. Description of the Related Art
The ESD robustness of CMOS integrated circuits (IC) has been found to be seriously degraded due to deep-submicron CMOS technologies. To improve the ESD robustness of the output transistors, the ESD-implant process and the silicide-blocking process have been widely implemented in the deep-submicron CMOS technologies. In addition to the process modification to improve the ESD robustness of the output buffers, the symmetrical layout structure had been emphasized to realize the large-dimension output transistors by ensuring the uniform turn-on phenomenon along the multiple fingers of the output transistor. To further enhance the uniform turn-on phenomenon among the multiple fingers of the output transistors, a gate-coupling design had been reported to achieve uniform ESD power distribution on large-dimension output transistors.
General circuit diagrams of the output cell, input cell, and I/O bidirectional cell in a cell library are shown in FIGS.
1
(
a
)-(
c
), respectively. In a general application, the output buffers in a cell library have different driving specifications. For instance, the output buffers in a typical library may have the different driving capabilities of e.g., 2 mA, 4 mA, 8 mA, or 24 mA. To meet these different types of current specification, different numbers of fingers in the MOS device of the cell are provided to drive current to, or sink current from, the pad. An example of the finger numbers of the different I/O cells in a 0.35-&mgr;m cell library used to provide the driving/sinking current are shown in TABLE 1.
TABLE 1
Current
Finger Number
Specification
xp
xn
yp
yn
input cell
0
0
14
14
4 mA
2
1
12
13
8 mA
4
2
10
12
10 mA
5
3
9
11
14 mA
7
4
7
10
18 mA
9
5
5
9
24 mA
12
6
2
8
Wherein W/L=35 &mgr;m/0.5 &mgr;m for each finger, and the xp (xn) is the number of fingers in the output PMOS (NMOS) layout, which are used to generate the output current to the pad.
However, the cell layouts of the output buffers with different driving capabilities are all drawn in the same layout style and area for programmable application. To adjust different output sinking (driving) currents of the output buffer, different number of fingers of the poly gates in the output NMOS (PMOS) are connected to the ground (VDD). The general layout of the NMOS device in the output cell with the used and unused fingers is shown in FIG.
2
(
a
). The schematic circuit diagram of the layout of FIG.
2
(
a
) is shown in FIG.
2
(
b
), where the used NMOS finger is marked as Mn
1
and the unused MOS fingers are lumped as Mn
2
. To provide a small output current, only a poly gate (used MOS finger) is connected to the pre-buffer circuit to control the NMOS (PMOS) on or off. The other poly gates are connected to VSS (VDD) to keep them off in the layout of FIG.
2
(
a
). Such layout structure has been widely used in IC products, especially in the digital IC's.
Due to the asymmetrical connection on the poly-gate fingers of the output NMOS in the layout, the ESD turn-on phenomenon among the fingers becomes quite different even if the layout is still symmetrical. When such an I/O cell with a small output current driving ability is stressed by ESD, the used NMOS Mn
1
is often turned on first due to the transient coupled voltage on its gate. As seen in FIG.
2
(
b
), the ESD voltage applied to the pad is coupled to the gate of Mn
1
and Mn
2
by the parasitic drain-to-gate overlapped capacitance (see the dashed line as shown in FIG.
2
(
b
)). The coupled gate voltage is kept at the gate of Mn
1
by the pre-buffer circuit, but the coupled voltage at the gate of Mn
2
is conducted to VSS. Therefore, the Mn
2
(with larger device dimension which is designed to protect Mn
1
) still remains off but the Mn
1
(with a smaller device dimension) is turned on to bypass the ESD current from the pad to VSS. This generally causes a very low ESD level for the output buffer, even the output buffer has a large device dimension in total (Mn
1
+Mn
2
).
The human body model (HBM) ESD level of an I/O cell library with different driving current specification but the same layout area and layout style is shown in TABLE 2.
TABLE 2
HBM
2 mA
4 mA
8 mA
12 mA
24 mA
ESD Stress
Buffer
Buffer
Buffer
Buffer
Buffer
VDD (−)
1.5 KV
2 KV
2.5 KV
>2.5 KV
>2.5 KV
ND Mode
VSS (+)
1.0 KV
1.5 KV
2.0 KV
>2.5 KV
>2.5 KV
PS Mode
The test data for two worst cases of ESD-testing pin combinations under the PS-mode ESD test and ND-mode ESD test are listed in Table 2 for the I/O cells with different output current specifications. According to the data of Table 2, it is concluded that when the output cell has a higher output current driving ability, the ESD level is also higher. However, the I/O cell with an output current of 2 mA only has an ESD level of 1 kV, even if the total (Mn
1
+Mn
2
) device dimension in every cell is the same. To verify the location of ESD damage on the I/O cell with a smaller output current, the ESD-stressed IC was de-layered to find the failure location.
The failure locations were found to locate at the Mn
1
device of the I/O cell. However, the Mn
2
in the same I/O cell was not damaged by the ESD stress. The detailed analysis on this failure issue is described in the paper by H. -H. Chang, M. -D. Ker and J. -C. Wu, “Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology,” Solid-State Electronics, vol. 43, pp. 375-393, February 1999. This creates a challenge to provide one set of I/O cells with better ESD level. Typically, the HBM ESD level of every I/O cell should be greater than 2 kV under any ESD-testing pin combination.
To improve ESD level of the I/O cells with different output current driving abilities, the descriptions of the gate-coupled technologies had been reported in publications by, e.g., C. Duvvury and R. N. Rountree, “Output buffer with improved ESD protection,” U.S. Pat. No. 4,855,620 (August, 1989); C.-D. Lien, “Electrostatic discharge protection circuit,” U.S. Pat. No. 5,086,365 (February, 1992) M.-D. Ker, C.-Y Wu, T. Cheng, C.-N. Wu, and T.-L. Yu, “Capacitor-couple ESD protection circuit for submicron CMOS IC,” U.S. Pat. No. 5,631,793 (May, 1997); and H.-H. Chang, M.-D. Ker, K. T. Lee, and W.-H. Huang, “Output ESD protection using dynamic-floating-gate arrangement,” U.S. Pat. No. 6,034,552 (March, 2000).
One of such gate-coupled designs is shown in
FIG. 3
(U.S. Pat. No. 5,631,793), where the unused Mn
2
(Mp
2
) in the I/O cell with small output current driving ability is connected to VSS (VDD) through the additional resistor Rw
2
(Rw
1
). An additional capacitor Cn (Cp) is added and connected from the pad to the gate of Mn
2
(Mp
2
) to generate the coupling effect. When a positive (negative) ESD voltage in the PS-mode (ND-mode) ESD test condition is applied to the pad, the overstress voltage is coupled to the gate of Mn
2
(Mp
2
) through the added capacitor Cn (Cp). The coupled voltage at the gate of Mn
2
(Mp
2
) is kept longer in time by the resistor Rw
2
(Rw
1
), therefore the unused Mn
2
(Mp
2
) with larger device dimension in the cell layout can be triggered on to discharge the ESD current. So, the gate-coupled technique is used to turn on the Mn
2
and Mp
2
to discharge ESD current before the Mn
1
(Mp
1
) is damaged by ESD. Because the Mn
2
and Mp
2
often have much larger device dimensions (channel width of several hundreds of micron), they can sustain a higher ESD stress. The more detailed description on the gate-coupled design is provided in the paper by M.-D. Ker, C.-E. Wu, and H.-H. Chang, “Capacitor-couple ESD protection circuit for deep
Jiang Hsin-Chin
Ker Ming-Dou
Peng Jeng-Jie
Industrial Technology Research Institute
Intellectual Property Solutions, Inc.
Sefer Ahmed N.
LandOfFree
ESD protection design with turn-on restraining method and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with ESD protection design with turn-on restraining method and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ESD protection design with turn-on restraining method and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3291118