ESD protection circuit with self-triggered technique

Details ESD protection circuit with self-triggered technique ESD protection circuit with self-triggered technique

2002-12-23

2004-06-01

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S355000, C257S357000, C257S370000

Reexamination Certificate

active

06744107

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to ESD protection circuits with self-triggered technique, and particularly to ESD protection circuits uniformly triggered.
2. Description of the Related Art
Electrostatic discharge (ESD) is a transient process of high energy transformation from external to internal of an IC when the IC is floated. Total discharge process takes about 100 ns. Also, several hundred or even several thousand volts are transferred during ESD stress. Such high voltage transformation will break down the gate oxide of an input stage and cause circuit error. As the thickness of gate oxide is scaled down constantly, it is more and more important that a protected circuit or device must be designed to protect the gate oxide and to discharge ESD stress.
Models related to ESD stress are divided into human body model (HBM), machine model (MM) and charged device model (CDM). For commercial IC products, the general ESD specification is required that IC products must pass these tests, for example, HBM ESD stress of greater than +/−2 kV, MM ESD stress of greater than +/−200V and CDM ESD stress of greater than +/−1 kV, respectively. In order to sustain such high ESD voltage, efficient and robust protection circuits, usually requiring large layout dimensions, should be used.
To achieve the above objective, some protection circuits have been proposed:
(1)Gate Grounded NMOS and Gate to VDD PMOS
A gate grounded NMOS and a gate shorted to VDD PMOS used as protection circuits for the input/output pad are shown in FIG.
1
. In normal operation, the ESD protection circuits are in a non-conductive state so that they do not interfere with the voltage level at the input/output pad. In all process generations of CMOS technology, the breakdown voltage of drain junction is almost smaller than that of gate oxide, a basic characteristic in the design of ESD protection circuits. The difference in the breakdown voltage between drain junction and gate oxide gets smaller as the gate length is shrunk. The design margin is also more and more narrow, that is to say, if the design or process technology is not optimum, the gate oxide will be damaged before the junction breakdown of drain terminal occurs. In the positive-to-VSS ESD zapping condition, the avalanche breakdown occurs in the drain terminal of the gate grounded NMOS Mn, and substrate current is also generated. The base volatge of parasitic lateral NPN (drain/substrate/source) is elevated because of the voltage drop across the substrate resistor due to the substrate current. As soon as the base/emitter junction is forward biased, the lateral NPN will be triggered to bypass ESD current. Also, the voltage of the input/output pad will be clamped at the holding voltage of the lateral NPN. In the negative-to-VSS ESD zapping condition, parasitic diode Dn (P_sub
+_drain) is forward biased to bypass ESD current and this process is independent of any breakdown mechanism. In the negative-to-VDD ESD zapping condition, avalanche breakdown occurs in the drain terminal of gate shorted to VDD PMOS Mp. Then the parasitic lateral PNP (drain
_well/source) is forward biased to bypass ESD current because of the same mechanism as the gate grounded NMOS Mn. In the positive-to-VDD ESD zapping condition, parasitic junction diode Dp (p+_drain
_well) is forward biased to bypass ESD current and this process is also independent on any breakdown mechanism.
(2)Input Protection Circuits with Equal Substrate Resistance
In traditional multi-finger NMOS layout technique, the center finger NMOS is usually turned on first because of its higher substrate resistance. As the center finger NMOS is turned on, the pad voltage will be kept at a lower potential and makes other finger inactive. All the ESD current will focus on the center finger NMOS, causing failure by over heating. For NMOS, using this layout style, the ESD level cannot be improved by increasing the layout area of the protection circuit. Thus, a new layout style, shown in
FIG. 2
, is proposed in U.S. Pat. No. 5,811,856 by TSMC. The new layout style is accomplished by adding P+ diffusion, adjacent to the source terminal of each finger NMOS device to make the base resistance of each parasitic bipolar transistor approximately equal. When an ESD zapping is applied to the input/output pad, the parasitic bipolar transistor will conduct simultaneously and with equal current, thus preventing over-heating from causing circuit failure.
(3)Gate Coupled Technique for ESD Protection
The ESD protection circuit, shown in
FIG. 3
, includes capacitors Cp
1
, Cn
1
, resistors Rp, Rn, a NMOS transistor Mn, and a PMOS transistor Mp. The NMOS Mn and the PMOS Mp transistors are configured with drains connected to the input/output pad
21
and sources connected to VSS and VDD respectively. The capacitors Cp
1
, Cn
1
are connected between the input/output pad
21
and the gates of the NMOS Mn and the PMOS Mp transistors. The resistors Rp, Rn are connected between VSS and VDD and the gates of the NMOS Mn and the PMOS Mp transistors. The values of the capacitors Cp
1
, Cn
1
and the resistors Rp, Rn can be tuned for coupling a portion of voltage to the gates of the NMOS Mn and the PMOS Mp transistors only under ESD zapping. Using the present protection circuit, the triggered voltage of ESD protection device can be lowered to protect the thin gate oxide of the internal circuit as soon as possible. In addition, the disadvantage of non-uniform turning on NMOS also can be improved.
(4)Substrate Triggered Technique for ESD Protection
The present ESD protection circuit shown in
FIG. 4
, similar to gate coupled technique, also includes a capacitor C
1
, a resistor R
1
and a NMOS M
5
transistor. The NMOS transistor is configured with a drain connected to the input/output pad
8
and a source connected to VSS. The gate and the source of the NMOS MS transistor are shorted together. The capacitor C
1
is connected between the input/output pad
8
and the body of the NMOS MS transistor. The resistor R
1
is connected between VSS and the body of the NMOS M
5
transistor. The values of the capacitor C
1
and the resistor R
1
can be tuned for coupling a portion of voltage to the body of the NMOS M
5
transistor only under ESD zapping. Therefore, the parasitic NPN bipolar transistor can be triggered on without through avalanche breakdown mechanism. In addition, the triggered voltage of the NMOS transistor can be lowered and the disadvantage of non-uniform turning on for NMOS can be improved by using this technique.
The ESD protection circuits mentioned above usually require large layout dimension and can not be turned on uniformly. There is a need for an ESD protection circuit that turns on uniformly and saving layout area.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an ESD protection circuit with uniform turning on.
To achieve the above objects, the present invention provides an ESD protection circuit with self-triggered techniques.
The present invention provides a multi-finger NMOS in which a center finger device with the largest substrate resistance has its source coupled to all bases of the parasitic bipolar transistors of the other finger devices. When an ESD zapping occurs in an input/output pad, the center finger device is triggered on and results in a current to turn on the other finger devices.
The present invention provides a multi-finger NMOS in which a center finger device with the largest substrate resistance has its source coupled to all gates of the other finger devices. When an ESD zapping occurs in an input/output pad, the center finger device is triggered on and reduces the triggered voltages of the other finger devices.
The present invention provides a multi-finger NMOS in which a center finger device with the largest substrate resistance has its source coupled to all bases of the parasitic bipolar transistors of the other finger devices and to all gates of the other finger devices. When an ESD

Affiliated with

Also associated with

Rating

ESD protection circuit with self-triggered technique does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with ESD protection circuit with self-triggered technique, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ESD protection circuit with self-triggered technique will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3301270