ESD protection circuit for a semiconductor integrated circuit

Details ESD protection circuit for a semiconductor integrated circuit ESD protection circuit for a semiconductor integrated circuit

2002-03-15

2003-04-08

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S141000

Reexamination Certificate

active

06545321

ABSTRACT:

BACKGROUND OR THE INVENTION
1. Field of the Invention
This invention relates to an electrostatic discharge (ESD) protection Circuit for a semiconductor integrated circuit suitable for use in preventing the destruction of internal devices caused by an ESD surge and the likes This invention particularly relates to an ESD protection circuit for a semiconductor integrated circuit of which protection performance has been enhanced.
2. Description of the Related Art
Semiconductor integrated circuits (ICs) are required to be resistant to surge voltage and surge current that are caused by electrostatic discharge (ESD) that is loaded on the input/output pad of IC. In general, to meet this requirement, an ESD protection circuit is connected to the input/output pad of IC.
FIG. 1A
is a sectional view illustrating the structure of a prior art ESD protection circuit, and
FIG. 1B
is an equivalent circuit diagram thereof.
Referring now to
FIG. 1A
, in the prior art ESD protection circuit, a p-type epitaxial layer
102
is deposited onto a p-type semiconductor substrate
101
, and an N well NW
101
and a P well PW
101
are ford on its surface. On the surface of the boundary between the N well NW
101
and P well PW
1021
an n+ diffusion layer ND
102
is formed.
On the surface of the N well NW
101
, an n+ diffusion layer ND
101
is formed apart from the n+ diffusion layer ND
102
, while a p+ diffusion layer PD
101
is formed between the n+ diffusion layer ND
102
and n+ diffusion layer ND
101
. These diffusion layers are electrically isolated from each other by shallow trench isolation (STI) films.
On the other hand, an n+ diffusion layer ND
103
is formed apart from the n+ diffusion layer ND
102
on the surface of the P well PW
101
, and a p+ diffusion layer PD
102
is formed further away from the n+ diffusion layer ND
102
The n+ diffusion layer ND
103
and p+ diffusion layer PD
102
are electrically isolated by another STI film. A conductive film
104
is formed on a p-type epitaxial layer
102
between the n+ diffusion layer ND
102
and n+ diffusion layer ND
103
via a gate dielectric film (not shown). An n-channel MOS transistor NMOS is formed by this conductive film
104
serving as the gate electrode, the n+ diffusion layer ND
103
as the source and the n+ diffusion layer ND
102
as the drain.
An input/output pad I/O is connected to the n+ diffusion layer ND
101
and p+ diffusion layer PD
101
, while the conductive film
104
, n+ diffusion layer ND
103
and p+ diffusion layer PD
102
are connected to a ground terminal GND.
As shown in
FIG. 1B
, in such an ESD protection circuit, the p+ diffusion layer PD
101
, N well NW
101
and P well PW
101
constitute a transistor Tr
101
, while N well NW
101
, P well PW
101
and n+ diffusion layer ND
103
constitute a transistor Tr
2
. Namely, the p+ diffusion layer PD
101
, N well NW
101
, P well PW
101
and n+ diffusion layer ND
103
constitute a silicon controlled rectifier (SCR). The N well NW
101
and P well PW
101
have parasitic resistances Rnw and Rpw, respectively.
When a surge positive to the ground terminal GND is applied to the input/output pad I/O, a breakdown occurs between the drain (n+ diffusion layer ND
102
) and the channel (P well PW
101
) of the transistor NMOS, and then a trigger current Itrig flows from the n+ diffusion layer ND
101
to the ground terminal GND via the N well NW
101
, n+ diffusion layer ND
102
and P well PW
101
. As a result, the potential of the N well NW
101
becomes lower than that of the input/output pad I/O due to the parasitic resistance Rnw parasitizing the N well NW
101
, and the potential of the P well PW
101
becomes higher than that of the ground terminal GND due to the parasitic resistance Rpw parasitizing the P well PW
101
. Then the SCR, which comprises the p+ diffusion layer PD
101
, N well NW
101
, P well PW
101
and n+ diffusion layer ND
103
, is activated. At this time, a large current Iscr flows to the ground terminal GND from the input/output pad I/O. As a result, the urge applied to the input/output pad I/O runs away to the ground terminal without damage of its internal circuit.
Examples of such an ESD protection circuit are disclosed in Japanese Patent Publication Laid-Open No Hei. 10-50494 and Japanese Patent Publication Laid-Open No. Hei. 10-313110, U.S. Pat. No. 5,465,189, and “1990 Symposium on VLSI Technology 6B-5” p. 75-76, for example.
FIG. 2A
is a sectional view illustrating the structure of another prior art ESD protection circuit, and
FIG. 2B
is an equivalent circuit diagram thereof. Such a prior art ESD protection circuit is disclosed in U.S. Pat. No. 5,465,189, for example. Referring now to
FIGS. 2A and 2B
, the n+ diffusion layer ND
101
is not connected to the input/output pad I/O but the power supply voltage terminal VDD in this prior art ESD protection circuit. The input/output pad I/O is connected only to the p+ diffusion layer PD
101
. Except for this difference, this prior art ESD protection circuit has the same structure as that of the prior at ESD protection circuit shown in
FIGS. 1A and 1B
.
In the above prior art ESD protection circuits, there exists the drain (n+ diffusion layer ND
102
) of the transistor NMOS between the anode and the cathode of the SCR. Thus the distance Lscr between the anode and cathode becomes rather long, about 2-3 &mgr;m, even if the technology of the 0.18 &mgr;m-generation is applied to the gate, and a sufficiently good ESD performance is not obtained this is because the discharging capability of the SCR degrades, as distance Lscr becomes longer.
FIG. 3A
is a sectional view illustrating the structure of another prior art ESD protection circuit, and
FIG. 3B
is an equivalent circuit diagram thereof. Referring now to
FIGS. 3A and 3B
, compared with the prior art ESD protection circuit shown in
FIGS. 2A and 2B
, an n+ diffusion layer ND
104
is formed instead of the transistor NMOS and the p+ diffusion layer PD
102
, and a device isolation film STI is formed between the p+ diffusion layer PD
101
and the n+ diffusion layer ND
104
. The n+ diffusion layer ND
104
is connected to a ground terminal GND. Besides, the N well NW
101
extends to beneath the device isolation film STI between the p+ diffusion layer PD
101
and the n+ diffusion layer ND
104
. In the other parts of structure, this prior art ESD protection circuit is the same as the prior art ESD protection circuit shown in
FIGS. 2A and 2B
.
In the prior art ESD protection circuit shown in
FIGS. 3A and 3B
, the anode-cathode distance Lacr can be reduced because there is no n+ diffusion layer formed between the N well NW
101
and the P well FW
101
.
However, the prior art ESD protection circuits have the following drawbacks. In the ESD protection circuits shown in
FIGS. 1A
,
1
B and
FIGS. 2A
,
2
B, the breakdown in the boundary between the n+ diffusion layer ND
102
, that is the drain of the MOS transistor NMOS, and P well PW
101
become, the trigger voltage (Vtrig) of the SCR. In this case, the breakdown can be controlled by changing the structure of the MOS transistor NMOS, then, the trigger voltage of the SCR can be set at the value lower than the tolerance voltage of the circuit to be protected (not shown) being connected to the input/output pad I/O. However, the SCR must be large size to achieve the adequate ESD performance because of the poor discharge ability of the SCR due to large distance Lscr. AS the result, the parasitic capacitance of the ESD protection circuit becomes large, so the ESD protection circuit can use for a high-speed interface circuit.
Meanwhile, in the ESD protection circuit shown in
FIGS. 3A and 3B
, the distance Lscr can be reduced. But in this EST protection circuit, the breakdown in the boundary between the N well NW
101
and P well PW
101
determines the trigger voltage (Vtrig) of the SCR. The trigger voltage of the SCR cannot be set at t

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