ESD protection circuit

Details ESD protection circuit ESD protection circuit

2005-03-15

2005-03-15

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S361000, C257S363000

Reexamination Certificate

active

06867461

ABSTRACT:
The claimed invention discloses an ESD protection circuit that is applied to an IC with power-down-mode operation. When the IC goes into power-down-mode operation, leakage current and charging from the I/O pad to the VDD power line could be prevented by applying the present invention. Therefore, the malfunction of the IC can be avoided. There still have two ESD clamp circuits respectively connected between the VDD power line and the VSS power line and between ESD bus line and VSS power line, so as to achieve the whole chip ESD protection scheme. The present invention can prevent ESD protection circuit from resulting in leakage current or malfunction under power-down-mode operation, and moreover achieve whole chip ESD protection scheme.

REFERENCES:
patent: 5229635 (1993-07-01), Bessolo et al.
patent: 5287241 (1994-02-01), Puar
patent: 6770938 (2004-08-01), Fliesler et al.
patent: 6774438 (2004-08-01), Arai et al.
patent: 20010033003 (2001-10-01), Sawahata

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