ESD protection circuit

Details ESD protection circuit ESD protection circuit

2006-08-29

2006-08-29

Ngô, Ngân V. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S361000, C257S363000, C257SE27062

Reexamination Certificate

active

07098511

ABSTRACT:
The claimed invention discloses an ESD protection circuit that is applied to an IC with power-down-mode operation. When the IC goes into power-down-mode operation, leakage current and charging from the I/O pad to the VDD power line could be prevented by applying the present invention. Therefore, the malfunction of the IC can be avoided. There still have two ESD clamp circuits respectively connected between the VDD power line and the VSS power line and between ESD bus line and VSS power line, so as to achieve the whole chip ESD protection scheme. The present invention can prevent ESD protection circuit from resulting in leakage current or malfunction under power-down-mode operation, and moreover achieve whole chip ESD protection scheme.

REFERENCES:
patent: 6144542 (2000-11-01), Ker et al.
patent: 2002/0064007 (2002-05-01), Chang et al.
patent: 2003/0116806 (2003-06-01), Kato
patent: 2004/0232492 (2004-11-01), Ker et al.
patent: 2005/0078419 (2005-04-01), Stockinger et al.

Affiliated with

Also associated with

Rating

ESD protection circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with ESD protection circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ESD protection circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3696298