Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-16
2004-12-28
Brock, II, Paul E (Department: 2815)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S633000, C438S637000
Reexamination Certificate
active
06835650
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electrostatic discharge and electrical overstress protection devices and methods of fabricating same. More particularly, the present invention relates to protection devices having charge dissipating structures within the electrostatic discharge and electrical overstress protection devices.
2. State of the Art
Electrostatic discharge (hereinafter “ESD”) and electrical overstress (hereinafter “EOS”) are two common phenomenon that occur during human or mechanical handling of semiconductor integrated circuitry (hereinafter “IC”) devices. The input pins to an IC device are highly sensitive to damage from the voltage spike of an ESD, which can reach potentials in excess of hundreds of volts. If a charge of this magnitude is brought into contact with a pin of an IC device, a large flow of current may surge through the IC device. Although this current surge may be of limited energy and duration, it can cause a breakdown of insulating barriers within the IC device (usually gate oxide insulating barriers of an MOS (metal-oxide-semiconductor) IC device). This breakdown of the insulating barriers within an IC device can result in permanent damage to the IC device and, once damaged, it is impossible to repair the IC device.
All pins of a MOS IC device must be provided with protective circuits to prevent such ESD voltages from damaging the insulating barriers (e.g., gate oxide) therein. The most common ESD protection schemes presently used in MOS IC devices rely on the parasitic bipolar transistors associated with an nMOS (n-channel or negative channel metal-oxide-semiconductor) device. These protective circuits are normally placed between the input and output pads (i.e., pin locations) on a semiconductor chip (which contains the IC device) and the transistor gates to which the input and output pads are electrically connected. With such protective circuits under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor of that nMOS device. This parasitic bipolar transistor operates in the snapback region under pin positive with respect to ground stress events. The dominant failure mechanism found in the NMOS protection device operating in snapback conditions is the onset of second breakdown. Second breakdown is a phenomena that induces thermal runaway in the IC device wherever the reduction of the ESD current is offset by the thermal generation of carriers. Second breakdown is initiated in an IC device under stress, known as electrical overstress or EOS, as a result of self-heating. The peak nMOS device temperature at which second breakdown is initiated is known to increase with the stress current level. The time required for the structure to heat-up to this critical temperature is dependent on the device layout and stress power distributed across the device.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of IC devices are ongoing goals of the computer industry. The advantage of increased miniaturization of components include: reduced-bulk electronic equipment, improved reliability by reducing the number of solder or plug connections, lower assembly and packaging costs, and improved circuit performance. In pursuit of increased miniaturization, IC devices have been continually redesigned to achieve ever higher degrees of integration, which has reduced the size of the IC device. However, as the dimensions of the IC devices are reduced, the geometry of the circuit elements have also decreased. In MOS IC devices, the gate oxide thickness has decreased to below 10 nanometers (nm), and breakdown voltages are often less than 10 volts. With decreasing geometries of the circuit elements, the failure susceptibility of IC devices to ESD and EOS increases, and, consequently, providing adequate levels of ESD/EOS protection, has become increasingly more difficult.
An exemplary method of fabricating an ESD/EOS protection structure (i.e., transistor) is illustrated in
FIGS. 29-38
.
FIG. 29
illustrates a first intermediate structure
200
in the production of a transistor. This first intermediate structure
200
comprises a semiconductor substrate
202
, such as a lightly doped P-type silicon substrate, which has been oxidized to form thick field oxide areas
204
and exposed to an implantation processes to form an n-type source region
206
and an n-type drain region
208
. A transistor gate member
212
is formed on the surface of the semiconductor substrate
202
residing on a substrate active area
214
spanned between the source region
206
and the drain region
208
. The transistor gate member
212
comprises a lower buffer layer
216
separating a gate conducting layer
218
of the transistor gate member
212
from the semiconductor substrate
202
. Transistor insulating spacer members
222
are formed on either side of the transistor gate member
212
. A cap insulator
224
is formed on the top of the transistor gate member
212
. An insulative barrier layer
226
is disposed over the semiconductor substrate
202
, the thick field oxide areas
204
, the source region
206
, the drain region
208
, and the transistor gate member
212
.
As shown in
FIG. 30
, an etch mask
232
is patterned on the surface of the insulative barrier layer
226
, such that openings
234
in the etch mask
232
are located substantially over the source region
206
and the drain region
208
. The insulative barrier layer
226
is then etched through openings
234
to form vias
236
which expose at least a portion of the source region
206
and the drain region
208
, as shown in FIG.
31
. The etch mask
232
is then removed, as shown in
FIG. 32. A
first conductive material
238
is deposited over the insulative barrier layer
226
to fill the vias
236
, as shown in FIG.
33
. The first conductive material
238
is planarized, as shown in
FIG. 34
, to electrically separate the first conductive material
238
within each via
236
(see FIG.
33
), thereby forming contacts
242
. The planarization is usually performed using a mechanical abrasion process, such as chemical mechanical planarization (CMP).
A deposition mask
244
is patterned on the insulative barrier layer
226
, having openings
246
over the contacts
242
, as shown in
FIG. 35. A
second conductive material
248
is deposited over the deposition mask
244
to fill the deposition mask openings
246
, as shown in FIG.
36
. The second conductive material
248
is planarized, as shown in
FIG. 37
, to electrically separate the second conductive material
248
within each deposition mask opening
246
(see FIG.
35
). The planarization is usually performed using a mechanical abrasion, such as a CMP process. The deposition mask
244
is then removed to leave the second conductive material forming a source contact metallization
252
and a drain contact metallization
254
, as shown in FIG.
38
.
Although methods as described above are used in the industry, it is becoming more difficult to control the proper alignment of the etch mask
232
for the formation of the contacts
242
, as tolerances become more and more stringent. For example, as shown in
FIGS. 39 and 40
, misalignment of the etch mask
232
can occur. Thus, as shown in
FIG. 40
, when the insulative barrier layer
226
is etched through the misaligned etch mask
232
to form a first via
256
and a second via
258
, the etch forming the first via
256
can destroy a portion of the transistor insulating spacer member
222
and/or the cap insulator
224
to expose the gate conducting layer
218
of the transistor gate member
212
. Thus, when a conductive material (not shown) is deposited in the first via
256
, the gate conducting layer
218
will short, rendering the transistor ineffectual. Furthermore, the misaligned etch mask
232
can also result in the second via
258
exposing a portion of the thick field oxide area
204
. However, since the etch to form the second via
Brock II Paul E
Micro)n Technology, Inc.
TraskBritt
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