Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-21
2002-11-12
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000, C257S357000, C257S358000, C257S359000, C257S360000, C257S361000, C257S362000, C257S363000
Reexamination Certificate
active
06479870
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Serial No. 89123687, filed Nov. 9, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a semiconductor device comprising a salicide layer. More particularly, this invention relates to self-aligned silicide (salicide) layers isolated by a shallow trench isolation for the purpose of saving one salicide block photomask.
2. Description of the Related Art
During or after the fabrication process of an integrated circuit (IC) such as the dynamic random access memory (DRAM) and the static random access memory (SRAM), the electrostatic discharge is a major reason for the damage of the integrated circuit. For example, when one walks on a carpet in the environment with a high relative humidity (RH), hundreds to thousands of electrostatic voltages are carried. When the relative humidity is low, the electrostatic voltage as high as tens of thousands volts can be carried. When these electrostatic charges are in contact with a chip, a discharge is very like to damage the chip to cause the device failure.
FIG. 1
shows an electrostatic discharge (ESD) device structure with a salicide layer isolated by a salicide block. The ESD device structure comprises a P type substrate
10
, a drain region
12
, a first source region
14
, a second source region
16
, a first gate
18
and a second gate
20
. The drain region
12
, the first source region
14
, the second source region
16
are formed by doping N+ type ions into the P type substrate
10
. The first and second gates
18
and
20
are located between the drain region
12
and the first source region
14
, and between the first source region
14
and the second source region
16
, respectively. On the surfaces of the drain region
12
, the first and second source regions
14
and
16
, and the first and second gates
18
and
20
, a salicide layer
22
is formed. A metal layer
24
is further formed to connect the drain region
12
, the first source region
14
and the second source region
16
.
To enhance the capability of the electrostatic discharge, a salicide block
26
is formed surrounding the salicide layer
22
on the drain region
12
, so that the salicide layer
22
on the drain region
12
is isolated from the first and second gates
18
and
20
. As a result, the effect of the local heating occurring at the drain junction upon the contact metal of the drain region can be eliminated. However, the formation of the salicide block
26
requires an additional photomask, so that the fabrication cost and time are raised.
SUMMARY OF THE INVENTION
The invention provides a electrostatic discharge (ESD) device with a salicide layer isolated by a shallow trench isolation instead of being isolated by the salicide block photomask to eliminate the effect of local heating in the drain junction upon the metal contact.
The ESD device comprises a P type substrate, in which an N well is formed. A gate is formed in the P type substrate out of the N well. A shallow trench isolation is formed in the N well to isolate a portion of the N well. A source region is formed in the P type substrate next to the gate, and a first drain region is formed in the junction of the P type substrate and the N well between shallow trench isolation and the gate. A second drain region is formed in the portion of the N well isolated by the shallow trench isolation. A salicide layer is formed on the gate, the source region, the first drain region and the second drain region, while the salicide layer on the second drain region is isolated from that on the first drain region by the shallow trench isolation.
In another embodiment of the invention, in a P type substrate on which an N well is formed, a P well is further formed in the N well. A gate is formed on the N well out of the P well. A shallow trench isolation is formed in the P well to isolate a central portion of the P well. A source region is formed in the N well and a first drain region is formed in the junction of the P well and the N well between the shallow trench isolation and the gate. A second drain region is formed in the portion of the P well isolated by the shallow trench isolation. A salicide layer is formed on the source region, the gate, the first drain region and the second drain region, while the salicide layer on the second drain region is isolated from that on the second drain region by the shallow trench isolation.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 6034388 (2000-03-01), Brown et al.
patent: 6114226 (2000-09-01), Chang et al.
patent: 6211001 (2001-04-01), Hsu
patent: 6310380 (2001-10-01), Cai et al.
Chen Shiao-Shien
Huang-Lu Shiang
Tang Tien-Hao
Elms Richard
J.C. Patents
Menz Douglas M
United Microelectronics Corp.
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