ESD device layout for effectively reducing internal circuit...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S355000, C257S360000, C257S356000, C257S357000, C257S363000, C257S389000, C257S401000, C257SE23070, C257SE23151, C257SE29026, C257SE29120, C361S056000

Reexamination Certificate

active

07855419

ABSTRACT:
An improved layout pattern for electrostatic discharge protection is disclosed. A first heavily doped region of a first type is formed in a well of said first type. A second heavily doped region of a second type is formed in a well of said second type. A battlement layout pattern of said first heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. A battlement layout pattern of said second heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. By adjusting a distance between the battlement layout pattern of a heavily doped region and a edge of well of said second type, i.e. n-well, a first distance will be shorter than what is typically required by the layout rules of internal circuit; and a second distance will be longer than the first distance to ensure that the I/O device have a better ESD protection capability. Accordingly, by properly adjusting the breakdown voltage of ESD device within I/O circuit, i.e. adjusting the distance between the edge of n-well and the battlement layout pattern of heavily doped regions, it will help to reduce the chip area and improve the ESD reliability.

REFERENCES:
patent: 5742083 (1998-04-01), Lin
patent: 5763919 (1998-06-01), Lin
patent: 6707113 (2004-03-01), Kobayashi
patent: 6713818 (2004-03-01), Kodama
patent: 7129546 (2006-10-01), Ker et al.
patent: 2005/0029597 (2005-02-01), Worley

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