ESD damage immunity buffer

Details ESD damage immunity buffer ESD damage immunity buffer

1999-12-14

2001-05-08

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S173000, C257S359000, C257S363000

Reexamination Certificate

active

06229183

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit (IC) protection technique. More particularly, the present invention relates to an electrostatic discharge immunity buffer that ensures the triggering of an ESD protection circuit prior to the buffer during an ESD event.
2. Description of the Prior Art
CMOS (Complementary Metal Oxide Semiconductor) transistors are used to increase the working speed of integrated circiuts (ICs). CMOS transistors also enhance IC performance and lower the cost of each chip. In order to reduce the hot carrier effect, MOS devices have LDD structures (Lightly Doped Drain). Additionally, a “salicide” process has been developed to reduce a spreading resistance between a source or a drain and a gate. However, these processes can lead to undesired results; namely, ICs can be damaged by electrostatic discharge (ESD), making reliability a concern. ESD influences the performance of ICs in measurement, fabrication, and use. Therefore, protecting ICs from ESD damage is extremely important.
As the size of ICs decreases, the ability to protect them from ESD damage becomes more difficult. One solution is an ESD-implant process. As applied in the CMOS process, two MOS devices are formed, wherein one MOS device has LDD structures, while the other doesn't. The MOS device having LDD structures is used in an internal circuit, and the other one is used for input/output (I/O). However, the junction between a source and a drain region of the MOS device that doesn't have LDD structures and a substrate is deeper. This will cause ions in the source or the drain regions to diffuse laterally. Thus, the channel length of the MOS device must be long so as to provide adequate protection from ESD damage.
In addition, a silicided-diffusion blocking process has also been proposed to protect MOS devices from the damage caused by ESD. This process removes the silicided diffusion regions in the source and the drain regions of a MOS device so that the sheet resistance is increased. Thus, the peak current during the ESD event is limited. This results in better protection to MOS devices.
Additionally, combining the silicided-diffusion blocking process and the ESD-implant process can effectively increase the protection of CMOS ICs from damage due to ESD.
However, an additional ESD-implant mask is added in the ESD-implant process described above. The number of steps in the process and the cost are therefore increased. Further, the ESD-implant process is complex, and the salicide processing may pollute the environment. This leads to low production yield.
SUMMARY OF THE INVENTION
Accordingly, the object of the present invention is to provide an ESD damage immunity buffer offering improved protection to CMOS ICs from damage caused by an ESD event.
To achieve the above-mentioned object of the invention, the present invention provides an ESD damage immunity buffer formed upon a semiconductor substrate, comprising: a gate, a first doped region, a second doped region, a third doped region, and a resist layer. The ESD damage immunity buffer, which is in parallel with an ESD protection circuit, is connected to a pad and the circuit grounding node. The gate is formed on the semiconductor substrate, and the first doped region and the second doped region are formed adjacent to the region below the gate in the semiconductor substrate and electrically coupled to the ground. The third doped region is formed in the semiconductor substrate and electrically coupled to the pad. Further, a resist layer is formed upon the semiconductor substrate and connects the third doped region to the second doped region, wherein said resist layer ensures a triggering of the ESD protection circuit prior to the ESD damage immunity buffer during an ESD event.
It is noted that the resist layer between the third doped region and the second doped region provides resistance against current flowing through the buffer. In other words, the ESD stress is released by an ESD protection circuit so that the internal circuit is protected.
Additionally, the ESD damage immunity buffer isn't destroyed by the “salicide” process. Moreover, the ESD damage immunity buffer is formed by layout, therefore the processes aren't as complex as those of the prior art. There is no increase in cost, either.
According to an example of the present invention, the resist layer connecting the second doped region to the third doped region is a well region in the semiconductor substrate.
According to the other example of the present invention, the resist layer connecting the second doped region to the third doped region is a polysilicon layer in the semiconductor substrate.
According to another example of the present invention, the resist layer connecting the second doped region to the third doped region is a barrier layer in the semiconductor substrate.


REFERENCES:
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patent: 5430602 (1995-07-01), Chin et al.
patent: 5440151 (1995-08-01), Crevel et al.
patent: 5440162 (1995-08-01), Worley et al.
patent: 5449939 (1995-09-01), Horiguchi et al.
patent: 5623387 (1997-04-01), Li et al.
patent: 5814865 (1998-09-01), Duvvury et al.
patent: 5850094 (1998-12-01), Kato et al.
patent: 6054736 (2000-04-01), Shigehara et al.

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