Error test for an address decoder of a non-volatile memory

Details Error test for an address decoder of a non-volatile memory Error test for an address decoder of a non-volatile memory

2007-11-27

2007-11-27

Pham, Lý Duy (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S189060, C365S189070, C365S189110

Reexamination Certificate

active

11291478

ABSTRACT:
A non-volatile memory includes word lines providing access to memory cells, a word-line decoder applying an activation signal corresponding to an input address to a word line, a converter reproducing the activation signal on outputs by lowering its voltage level, and an encoding circuit that includes transistors with a switching threshold that is lower than the voltage level of the outputs and coupled so as to generate an output address specific to an activated word line if this word line is the only one activated, such that a test circuit generates an error signal if the input address differs from the output address. In such a configuration, the area of silicon occupied by a test circuit can be reduced.

REFERENCES:
patent: 5265056 (1993-11-01), Butler et al.
patent: WO 03/003379 (2003-01-01), None

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