Error signal calculation from a Viterbi output

Details Error signal calculation from a Viterbi output Error signal calculation from a Viterbi output

1999-09-01

2002-11-19

Chung, Phung M. (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S799000

Reexamination Certificate

active

06484286

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to error detection in a read channel. More specifically, a system and method for precomputing an error signal from a Viterbi output is disclosed.
BACKGROUND OF THE INVENTION
FIG. 1A
is a block diagram of a magnetic disk reading system including circuitry for reading an analog signal from a magnetic storage disk. An analog signal is recovered from a detector and input to analog front end
202
. Analog front end
202
includes various analog processing components that condition the signal from the detector for deriving a digital signal from the analog data. For example, analog front end
202
may include a boost filter for boosting the high frequency component of the signal from the detector. Analog front end
202
may also include an adjustable gain amplifier that amplifies the signal. In addition, analog front end
202
may include an adjustable timing loop that recovers a clock from the signal or adjusts a clock to be synchronized to the analog data signal read from the detector. Analog front end
202
may also include an adaptive equalizer for equalizing the analog signal.
Some or all of the above-mentioned analog components may be adaptable based on the signal that is being read. Different disk drive systems tend to have different channel transfer functions or responses when data is read from disk. In fact, a single disk or disk drive may change as the disk or disk drive ages and experiences wear. As a result, it is often necessary to adjust the parameters of the devices in the analog front end such as the boost filter, the gain, the amplifier, the timing recovery circuit, and the equalizer to adapt to changes in the disk. Also, these various components may need to be adapted to vary for changes that occur in reading different regions of a single disk.
The output from analog front end
202
is input to an analog-to-digital converter (ADC)
204
. The output of analog-to-digital converter
204
in one embodiment is a six-bit output that forms part of a sequence, Z: z
1
, z
2
, . . . z
n
, z
n+1
. . . , Z is the data sequence that results from the data that was originally written to the disk being transformed by the data channel. The six-bit representation of the elements of the input sequence at the output has more precision than the input data itself because it has been transformed by intersymbol interference and other effects of the channel.
The digitized output of ADC
204
is input to a Viterbi detector
206
. Viterbi detector
206
is configured to read the six-bit output from the analog-to-digital converter and to determine, based on the sequence of data, the most likely input sequence that produced the sequence. The Viterbi detector may do that by determining the Euclidean distance from a given output sequence to different possible output sequences that correspond to various input sequences. The possible output sequence that is the closest to the detected output sequence is determined to be the correct output sequence. In doing this, the Viterbi detector must look at more than one element of the output sequence of the analog-to-digital converter because the transfer function of the channel and analog front end
202
is generally a function of more than one element in the data sequence. For example, one type of coding, EPR
4
, has a transfer function that is 1+D−D
2
−D
3
. Thus, Viterbi detector
206
operates on the raw digitized output from the ADC to produce a recovered data sequence corresponding to a most likely input sequence.
The performance of components in analog front end
202
, such as the equalizer and the timing recovery circuit, can be improved by adapting their characteristics using feedback from the output. To that end, an error signal that describes the difference between the raw digitized output and the recovered data signal is computed. Accordingly, the output of Viterbi detector
206
is sent to error signal calculation circuitry
208
. Error signal calculation circuitry
208
computes an error signal by subtracting the transformed output of Viterbi detector
206
from the corresponding output of ADC
204
. In addition, error signal calculation circuitry
208
may calculate other parameters such as a level signal. A level signal indicates whether an output is positive, negative, or zero and can be used in conjunction with the error signal to improve the performance of components in analog front end
202
.
The output of error signal calculation circuitry
208
is sent to a control parameter adjustment generator
210
. Control parameter adjustment generator
210
uses the signals calculated by error signal calculation circuitry
208
to compute parameters that can be used to improve the performance of, for example, the timing loop, the gain loop, the offset loop, the MR amplitude asymmetry loop, and the filter boost loop in analog front end
202
.
FIG. 1B
is a block diagram of an implementation of error signal calculation circuitry
208
. A recovered output signal
220
, a
n
, is received from Viterbi detector
206
and sent to circuitry
222
that applies a transfer function to the recovered output signal.
The transfer function applied by circuitry
222
typically relies on multiple terms in the sequence, A, of recovered output signals, a
1
, a
2
, . . . a
n
, a
n+1
. . . . Thus, circuitry
222
typically includes memory elements for storing a plurality of recovered output signals, a
n−1
, a
n−2
, a
n−3
, from Viterbi detector
206
, and also includes a processor or logic for applying a transfer function to the sequence of recovered output signals.
Circuitry
222
operates on a sequence of recovered output signals, a
n
, a
n−1
, a
n−2
, a
n−3
, to produce a transformed signal, x
n
. This transformed signal, x
n
, is used to compute an error signal, e
n
, and a level signal, level
n
. The error signal, e
n
, is computed by subtracting the transformed output signal, x
n
, from the raw digitized output signal, z
n
, (
224
) where z
n
represents the output signal corresponding to the recovered data signal, a
n
, from which the transformed signal, x
n
, was calculated. The level signal is calculated from the transformed output, x
n
, and simply indicates whether x
n
is positive, negative, or zero (
226
).
Because circuitry
222
uses a sequence of recovered output signals to calculate X
n
——for example, the EPR4 transfer function uses a
n
, a
n−1
, a
n−2
, and a
n−3
—there is a delay of several clock cycles while circuitry
222
waits to receive this sequence. Moreover, because the calculation of x
n
is relatively complex—requiring several multi-bit additions and subtractions—it typically requires multiple clock cycles to complete, even after the sequence of recovered output signals, a
n
, a
n−1
, a
n−2
, a
n−3
, has been received.
Thus, to compute an error signal, e
n
, circuitry
222
first waits several clock cycles to collect the sequence of recovered output signals, a
n
, necessary to calculate x
n
. This is followed by additional delay while the transfer function is applied to yield x
n
. And finally, additional delay occurs when x
n
is subtracted from the raw digitized output signal z
n
to yield e
n
.
Thus, while the above-described system is effective for disk reading schemes that utilize a simple read-channel target transfer function such as PRML or EPRML, it begins to lose its effectiveness as the complexity of the target transfer function increases, and each element of the read channel output sequence becomes a function of a greater number of input sequence elements. Computing the error from the input to the output in the manner described above for a system with a more complex transfer function, such as EPR
4
, requires the recovery of several output data points before the error can determined. This increases the latency of the system and reduces the effectiveness of the feedback loop.
Accordingly, a better method of calculating the error is needed to decrease the delay in the f

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