Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2008-07-29
2008-07-29
Baderman, Scott T (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S047300
Reexamination Certificate
active
10607517
ABSTRACT:
A high-performance, high-reliable backplane bus has a simple configuration and operation. An error reporting network (ERN) provides an inexpensive approach to collecting the error state of a whole system in a uniform and consistent way. The uniformity allows for simpler interface software and for standardized hardware handling of classes of errors. In a preferred embodiment, serial error registers are used, minimizing implementation cost and making the software interface to the serial registers much easier. Serial error information is transferred over a separate data path from the main parallel bus, decreasing the chance of the original error corrupting the error information. Each CPU is provided with a local copy of the entire body of error information. The redundancy minimizes the impact of a possible CPU failure and allows the CPUs to coordinate error recovery.
REFERENCES:
patent: 5410542 (1995-04-01), Gerbehy et al.
patent: 6131112 (2000-10-01), Lewis et al.
patent: 2001/0008021 (2001-07-01), Ote et al.
patent: 2002/0080930 (2002-06-01), Cho
patent: 2003/0101385 (2003-05-01), Lee
patent: 2004/0153870 (2004-08-01), Konz et al.
patent: 54071954 (1979-06-01), None
patent: 02/31656 (2002-04-01), None
Author not listed: “Mechanism for Capturing Failure Data with a Replaceable Machine Element”, IBM Technical Disclosure Bulletin, IBM Corp., vol. 37, No. 01, Jan. 1994, pp. 163-164.
Kieckhafer, R. et al.: “The MAFT Architecture for Distributed Fault Tolerance”, I.E.E.E. Transactions on Computers, IEEE, vol. 37, No. 4, Apr. 1988, pp. 398-405.
Sachs, M. W.: “Automatic Transfer of Sense Data to Channel”, IBM Technical Disclosure Bulletin, IBM Corp., vol. 25, No. 3B, Aug. 1982, pp. 1738-1739.
Johnson, D. B.: “Error Reporting in the Intel iAPX 432”, IEEE Comp. Soc. Press, 1984, pp. 24-28.
Kayfes Paul
Lewis Jason
Lloyd Stacey
Lynch John
Myers Mark
Baderman Scott T
Contino Paul F.
Fujitsu Siemens Computers LLC
Greenberg Laurence A.
Locher Ralph E.
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