Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-02-08
2001-10-09
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S759000, C714S763000
Reexamination Certificate
active
06301682
ABSTRACT:
BACKGROUND OF THE INVENTION
The data contents of memory systems are often protected in such a way that a plurality of redundant bits are additionally co-stored under the address of a data word. These bits are called check bits, K-bits or ECC-bits and arise by forming the parity sum over specific parts of the data word, which is usually referred to as EDC coding (“EDC” abbreviated for Error Detection Code). Upon readout of the memory word, the sub-parities are formed anew and compared to the allocated K-bits that are likewise readout. When there is equality for all K-bits, then it is concluded that the readout data word is error-free. Given inequality, conclusions about the kind of error are drawn from the pattern of the non-coincidence, what is referred to as the syndrome pattern.
Those K-bit positions that do not agree in said comparison are called syndromes. Specific syndrome patterns are decoded and the falsified bit position in the data word is thus potentially determined and corrected by inverting.
The formation of the K-bits (EDC encoding), the comparison of the K-bits, the decoding of the syndromes as well as the correction and potential alarm to a higher-ranking controller currently normally ensues with the assistance of specific controller modules, which are also referred to as EDC controllers below.
When a fault is then present in the memory system that causes an uncorrectable error, that is, a multi-bit error (for example, drive error or memory bit falsification error or memory module failure), this error can in fact be recognized by the error monitoring system with high probability, but only after the readout of the faulty data. This can be very late after the occurrence of the error under certain circumstances. The negative effects of the error can already be considerable at this late point in time.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved memory system.
In general terms the present invention is a memory system, wherein a respective check word is co-stored together with a data word. An error monitoring system generates the check word from the data word to be written in and from he write address according to a specific formation rule, what is referred to as the EDC code before the check word in common with the data word to be written in is stored under the write address. The error monitoring system also generates a check word anew according to the EDC code on the basis of a data word to be read out from the memory system. It compares the bits of the check word (K-bits) to the K-bits stored for the data word and, given inequality, draws conclusions about the type of error from the pattern of the equal and unequal K-bits, what is referred to as the syndrome pattern. Before storing a data word to be written under its write address, an internal read even it implemented, whereby the error monitoring system implements the error check as previously described.
In one embodiment of the present invention the error monitoring system co-involves the address in the EDC coding, that is, in the formation of the check word. What is particularly avoided as a result of this embodiment is that a DW is written under an unintended address due to a drive error (for example, addressing error) that affects the entire memory word and a DW stored in this memory cell is overwritten. In a second attempt, morever, the data to be stored can be deposited under another error-free write address and are thus not lost.
In a further embodiment of the present invention at least two separately driven memory units and a respective segment of the data word together with a segment of the check word is stored in each memory unit. The EDC code is selected such that the comparison yields an odd number of unequal K-bits given a one-bit error. An even number of unequal K-bits respectively contribute to the odd number from those segments of the check word that are not stored together with that segment of the data word in which the one-bit falsification is present.
What is particularly avoided as a result of this embodiment is that a DW segment is written under an unintended address due to a drive error (for example, addressing error) that affects a memory word segment covering this DW segment and a DW segment stored in this memory cell is overwritten. In a second attempt, moreover, the data to be stored can be deposited under another error-free write address and are thus not lost.
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IBM Technical Disclosure bulletin, vol. 34 No. 3, Aug. 1991, Memory Of Address Fault Detection In Embedded Memory, pp. 139-140.
Amanze Emeka J.
De'cady Albert
Schiff & Hardin & Waite
Siemens Aktiengesellschaft
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