Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1998-01-29
2000-03-28
Chung, Phung M.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
714746, 714 48, H03M 1300
Patent
active
060444835
ABSTRACT:
A method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip. The invention provides 84/72 ECC for computer systems having a four bit per chip memory configuration and 88/72 ECC for computer systems having an eight bit per chip memory configuration. Further embodiments provide downstream error notification propagation for the host computer system.
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Chen Chin-Long
Dell Timothy Jay
Kwan Wayne C.
Chung Phung M.
Ehrlich Marc A.
International Business Machines - Corporation
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