Error processing method and information processing apparatus

Details Error processing method and information processing apparatus Error processing method and information processing apparatus

2007-07-26

2011-10-04

Baderman, Scott (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S004500, C714S006100, C714S042000, C714S025000

Reexamination Certificate

active

08032794

ABSTRACT:
An error processing method processes an error generated on a bus of a CPU, by inputting a bus error that is generated on at least one of an instruction bus and a data bus of the CPU to the CPU by a bus error input part, counting the bus error by a bus error counter part of the CPU, and specifying a region of a memory part that is coupled to the CPU based on a value of the bus error counter part.

REFERENCES:
patent: 4924465 (1990-05-01), Matsubara et al.
patent: 5987585 (1999-11-01), Motoyama et al.
patent: 6757809 (2004-06-01), Yoshida
patent: 6823448 (2004-11-01), Roth et al.
patent: 7076719 (2006-07-01), Anjo et al.
patent: 2004/0139372 (2004-07-01), Moyer et al.
patent: 2005/0144551 (2005-06-01), Nahas
patent: 59-95500 (1984-06-01), None
patent: 06-242977 (1994-09-01), None
patent: 2004-516546 (2004-06-01), None
Japanese Office Action issued Apr. 26, 2011 in corresponding Japanese Patent Application 2006-269635.

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