Error detection/correction and fault detection/recovery – Pulse or data error handling – Data pulse evaluation/bit decision
Reexamination Certificate
1999-06-11
2002-04-16
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Data pulse evaluation/bit decision
C714S712000, C714S820000
Reexamination Certificate
active
06374374
ABSTRACT:
TECHNICAL FIELD
The invention relates to an error processing circuit for a receiving location of a system for transferring binary data in the form of pulse sequences.
BACKGROUND OF THE INVENTION
One form of a data transmission system is a CAN system. The term CAN stands for Controller Area Network. Further details in this respect can be found in the book “Controller Area Network: CAN” by Konrad Etschberger, Carl Hanser Publishing House 1994, ISBN No. 3-446-17596-2. Of interest in the present context are the sections on Protocol Properties on pages 25 and 26 and Data/Frame Format on pages 37 to 43.
Such CAN systems are employed for example in the field of motor vehicles.
There is a common supply voltage source for the CAN system, e.g., in the form of a motor vehicle battery delivering for instance a battery voltage of 12 V. Furthermore, each network node has an individual operating voltage source associated with each network node, which produces from the supply voltage a regulated operating voltage feeding the respective network node. Each operating voltage source delivers an operating potential, for example of 5 V, at a first terminal and a reference potential, for example ground potential or 0 V, at a second terminal.
The transmitting part of a network node has two resistors and two controllable electronic switches connected to the two lines of the double-line bus. One of these lines is connected via a first one of these resistors to the operating potential (5 V) and via a first one of these switches to the reference potential (0 V). The other line is connected via the second resistor to the reference potential (0 V) and via the second switch to the operating potential (5 V). For transmitting digital communications, the two switches are controlled synchronously either to a conducting state or to a non-conducting state. When the switches are controlled to the non-conducting state, the operating potential is present on one line and the reference potential is present on the other line. This switch state, for example, has the logic value “1” associated therewith. When the switches are controlled to the conducting state, the reference potential is present on one line and the operating potential is present on the other line. This switch state then has the logic value “0” associated therewith.
As the transmitting parts of all network nodes capable of transmission are connected in parallel with respect to the two lines, the potential ratio on the two lines, which is associated with logic value “0”, can be produced by closing the two switches of each of the transmissive network nodes. On the other hand, the non-conducting state of the two switches of each network node can be covered up by the conducting state of the two switches of another network node. For this reason, the logic value associated with a closed switch pair (logic value “0”) is referred to as dominant and the logic value associated with a non-conducting switch pair (logic value “1”) is referred to as recessive.
The receiving part of each network node capable of reception comprises a comparator comparing the respective potentials on the two lines with each other. Upon reception of a recessive bit (logic value “1”), for example, a positive potential is created at the output of the comparator, which has the logic value “1” associated therewith. Upon reception of a dominant bit (logic value “0”), a potential corresponding to the reference potential is present at the output of the comparator, which then has the logic value “0” associated therewith. The comparator thus constitutes a decoder for the potential relationships corresponding to the respective transmitted bit on both lines.
For reasons of redundance, the two lines are used in addition to system ground. The message information corresponding to the potential value of the respective bit transmitted is thus transferred both via the one line and via the other line. In case of failure of one of the lines, the further transmission operation can be restricted to the non-failed line. For detecting line failures, two additional comparators are provided, one thereof comparing the potential of one line and the other one thereof the potential of the other line with a mean potential that is between the operating potential and the reference potential.
There can occur different line failures or line faults or errors, for instance, in the form of short-circuits between the two lines, short-circuits towards system ground, short-circuits towards the operating potential source, short-circuits towards the supply voltage source or in the form of open lines. There are line errors that do not hinder secure decoding of the communications transmitted. There are other line errors against which specific measures need to be taken in order to still render possible correct decoding. More details in this respect can be found in DE 195 23 031 A1.
In a CAN network, the messages or communications are transferred in the form of pulse sequences or frames spaced apart in time. The usual CAN protocol provides that a minimum distance in time is present between the individual frames and that within one frame there must be no more than 11 recessive or dominant bits in succession.
It is known from DE 196 23 031 A to use, for a decoder on the receiving side, the three comparators mentioned hereinbefore, to examine the output signals thereof for the presence of specific line errors with the aid of an error recognition circuit and to decide, depending on the result of this comparison, the output of which one of these three comparators is to be connected to a data output of the receiving location via a multiplexer controlled by the error recognition circuit. When the comparator comparing the potential values of the two lines delivers the potential value of the dominant logic value “0” for a longer duration than permitted according to the CAN protocol, it is assumed that the two lines are either short-circuited with respect to each other or the first line has a short-circuit towards system ground, and the comparator used as data output is that one which compares the potential of the second line to a mean potential value. This means, as soon as the comparator comparing the potential values permanently has the dominant logic value “0” beyond the duration permitted by the CAN protocol, recourse is taken to the potential changes on the second line for decoding of the data received.
However, there are line faults or errors that are recognizable by a permanent dominant logic value “0” at the output of the comparator comparing the potential values of the two lines, but in case of which there are no more potential changes taking place on the second line. Such a case is present when the second line displays a short-circuit towards the operating voltage source (5 V) associated with or inherent with each network node. In case of such a line error too, the known circuit arrangement also takes recourse to the output of the comparator monitoring the second line with respect to potential changes. And as there are no more potential changes taking place, data decoding fails.
SUMMARY OF THE INVENTION
The invention provides an error processing circuit for a receiving location of a system for transferring binary data in the form of pulse sequences, wherein the system has a number of receiving locations connected via a double-line bus having a first line and a second line. A first logic value of the binary data is represented by a high potential value on the first line and a low potential value on the second line, and a second logic value of the binary data is represented by a low potential value on the first line and a high potential value on the second line. Within each pulse sequence, there must be no more than a predetermined number of equal data bits in succession.
The receiving location includes a data output, a decoder having three decoder outputs, a first decoder output associated with both lines delivers a first decoder output signal dependent on the difference between the potential values of both lines, a second decoder ou
Jorgenson Lisa
Seed IP Law Group PLLC
STMicroelectronics GmbH
Tarleton E. Russell
Tu Christine T.
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