Error log system for self-testing in very large scale integrated

Details Error log system for self-testing in very large scale integrated Error log system for self-testing in very large scale integrated

1988-06-21

1990-06-05

Fleming, Michael R.

Excavating

371 291, G06F 1100

Patent

active

049320289

ABSTRACT:
A VSLI chip is implemented with registers which log permanent and intermittent errors occurring within the chip as sensed by concurrent error detection circuitry (CED). If a fatal error is detected (one which would destroy the reliability of chip operations), then the chip is immobilized into a hold mode (freeze). Interrupts are signalled to a cooperating maintenance controller which can pass the error information to an external computer for display and for locating a faulty area.

REFERENCES:
patent: 4205301 (1980-05-01), Hisazawa
patent: 4209846 (1980-06-01), Seppa
patent: 4339657 (1982-07-01), Larson
patent: 4635214 (1987-01-01), Kasai
patent: 4726024 (1988-02-01), Guziak
patent: 4755997 (1988-07-01), Takahashi
patent: 4821269 (1989-04-01), Jackson
patent: 4829520 (1989-05-01), Toth

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