Error generation circuit for testing a digital bus

Details Error generation circuit for testing a digital bus Error generation circuit for testing a digital bus

1999-02-22

2000-04-11

Wright, Norman M.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 30, 714 48, G06F 1100

Patent

active

060498943

ABSTRACT:
In order to test a parallel digital bus, an integrated circuit adapted for coupling to the bus has a bus error generation circuit which generates and/or simulates bus error conditions on the bus. During test, an error command is loaded into a command register of the bus error generation circuit via the bus. The bus error generation circuit then decodes the command, and either: 1) generates an error condition on the bus during a subsequent bus cycle, or 2) simulates an error condition on the bus during a subsequent bus cycle. A status configuration register in the integrated circuit and status configuration registers in other devices on the bus are then read to determine whether the integrated circuit and other devices properly detected and/or handled the generated or simulated error. By providing a bus error generation circuit in the integrated circuits coupled to a bus inside a personal computer, built-in test of the personal computer is facilitated.

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