Error detector, semiconductor device, and error detection...

Details Error detector, semiconductor device, and error detection... Error detector, semiconductor device, and error detection...

2006-04-18

2006-04-18

Torres, Joseph (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07032161

ABSTRACT:
An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string was generated at the transmitter so that errors in the reception bit string is detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string. The reception bit string is inputted to the first feedback shift register in the same order in which the transmission bit string was generated, while the reception bit string is inputted to the second feedback shift register in reverse order to one which the transmission bit string was generated. Errors in the reception bit string are detected by comparing respective remainders obtained by the first and second feedback shift registers. This reduces the processing time required for the error detection and increases efficiency in detecting errors in transmitted data.

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Stephen B. Wicker “Error Control Systems for Digital Communication and Storage”, Prentice-Hall, 1995.
Stephen B. Wicker, “Error Control for Digital Communication and Storage”, Prentice-Hall, 1995, pp. 116-119.
Copy of the International Search Report for Application No. EP 99 10 9434; Date of Search: Apr. 18 2001; Examiner: C. Devergranne.

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