Error detector, semiconductor device, and error detection...

Details Error detector, semiconductor device, and error detection... Error detector, semiconductor device, and error detection...

1999-05-14

2002-12-10

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

06493844

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a detection of errors in data and, more particularly, to an error detector for detecting errors that occur in data under transmission.
The present invention relates to a semiconductor device comprising the error detector.
The present invention relates to an error detection method for detecting errors that occur in data under transmission.
2. Description of the Related Art
There are various factors which may cause errors in data being transmitted via transmission lines. For the detecting the errors, a transmitter in a communication system adds check data, under a given rule, to target data to be transmitted. A receiver in the communication system examines whether or not the transmitted data is in accordance with the rule and judges whether or not there are the presence of errors based on the result of the detection.
Out of error detection methods, the most prevalent one is a CRC (Cyclic Redundancy Check) method using a cyclic code. In the CRC error detection, the transmitter splits the target data to be transmitted into information bit strings of a specified length, represents each of the information bit strings in a polynomial, and divides it by a generator polynomial. The transmitter then generates the cyclic code by adding, as check bits, a remainder from the division to the information bit string and transmits the cyclic code to the receiver.
The receiver divides the received cyclic code by the same generator polynomial used at the transmitter to judge whether or not the presence of errors depending on whether or not the cyclic code is divisible.
FIG. 1
shows an exemplary communication system that performs the error detection by using the cyclic code. In the communication system, a transmitter
1
, and a receiver
2
are connected to each other via a radio transmission line
3
. The transmitter
1
and the receiver
2
correspond to, e.g., a base station and a mobile terminal for mobile communication such as a mobile phone, respectively.
The transmitter
1
has a coder
4
for coding data to be transmitted and a data modulating/transmitting unit
5
for modulating the coded data and outputting the modulated data to the radio transmission line
3
. The coder
4
is composed of a feedback shift register
6
.
The receiver
2
has a data receiving/demodulating unit
7
for receiving the data transmitted via the radio transmission line
3
and demodulating the received data, and an error detector
8
for detecting errors in the demodulated data. The error detector
8
is composed of a feedback shift register
9
and an right/wrong output unit
10
for outputting an error detecting signal FLAG. The error detector
8
has been formed in a semiconductor device SEM with other communication functional elements.
As shown in
FIG. 2
, the feedback shift register
6
and the feedback shift register
9
are composed of identical circuits such as dividers conforming to a sixteenth-degree generator polynomial X
16
+X
12
+X
5
+1.
Each of the feedback shift registers
6
and
9
has a register unit
11
consisting of flip-flop circuits X
15
to X
0
(hereinafter referred to as F/F circuits X
15
to X
0
) connected in cascade, three EOR (Exclusive OR) circuits
12
a,
12
b,
and
12
c,
and switches S
1
and S
2
. In the register unit
11
, a shift direction has been set such that data is shifted from the F/F circuit X
0
to the F/F circuit X
15
. A clock signal CLK is connected to the clock terminal of each of the F/F circuits X
15
to X
0
such that shift operations are performed in synchronization.
The EOR circuit
12
a
receives an output of the F/F circuit X
15
and an input signal DIN
1
(or DIN
2
) and outputs the result of the operation to the F/F circuit X
0
. The EOR circuit
12
b
receives the output of the EOR circuit
12
a
and an output of the F/F circuit X
11
and outputs the result of the operation to the F/F circuit X
12
. The EOR circuit
12
c
receives the output of the EOR circuit
12
a
and an output of the F/F circuit X
4
and outputs the result of the operation to the F/F circuit X
5
.
The switch S
1
is for selectively connecting the output of the F/F circuit X
15
or the input signals DIN
1
and DIN
2
to the output signals DOUT
1
and DOUT
2
of the feedback shift registers
6
and
9
. The switch
2
is for feeding back the output of the EOR circuit
12
a
to the EOR circuits
12
b
and
12
c
and to the F/F circuit X
0
.
In the communication system shown in
FIG. 1
, the transmitter
1
performs coding and the receiver
2
performs the error detection as follows. By way of example, the following description will be given to the case where a 6-bit information bit string “01 0101” is transmitted.
FIG. 3
shows the respective states of the F/F circuits X
15
to X
0
when the feedback shift register
6
at the transmitter
1
is operated. Upon each receipt of the clock signal CLK, the feedback shift register
6
shifts the values held by the F/F circuits X
15
to X
0
to the left in the drawing, so that “STATE” is incremented by 1 upon each receipt of the clock signal CLK. That is, the individual F/F circuits X
15
to X
0
undergo transitions from “STATE 0” to “STATE 6” when viewed in the columnar direction.
In “STATE 0”, each of the F/F circuits X
15
to X
0
is reset to “0”.
In “STATE 1” through “STATE 6” shown in
FIG. 2
, the switch S
1
is switched to connect the input signal DIN
1
to the output signal DOUT, and the switch
2
is closed. Consequently, the information bit string “01 0101” inputted from the input signal DIN
1
is inputted to the feedback shift register
6
and outputted simultaneously to the output signal DOUT
1
.
The information bit string outputted to the output signal DOUT
1
is modulated by the data modulating/transmitting unit
5
and then transmitted to the receiver
2
via the radio transmission line
3
.
When the feedback shift register
6
has operated to reach “STATE 6”, the values “0100 0010 0001 0100” held by the respective F/F circuits X
15
to X
0
form a check bit string and the cyclic code “01 0101 0100 0010 0001 0100” enclosed in the bold rectangle of
FIG. 3
are generated from the information bit string and the check bit string.
An output of the check bit string is performed by operating the feedback shift register
6
and sequentially outputting the values held by the F/F circuits X
15
to X
0
in “STATE 6” to the output signal DOUT
1
. At this time, the switch S
1
is switched to connect the output of the F/F circuit X
15
to the output signal DOUT
1
, and the switch S
2
is open. By opening the switch S
2
, a “0” is inputted to each of the F/F circuit X
0
and the EOR circuits
12
b
and
12
c.
The check bit string outputted to the output signal DOUT
1
is modulated by the data modulating/transmitting unit
5
and then transmitted to the receiver
2
via the radio transmission line
3
.
The data receiving/demodulating unit
7
at the receiver
2
receives the modulated cyclic code (information bit string+check bit string) and sequentially demodulates it to the original cyclic code. The data receiving/demodulating unit
7
inputs the individual bits of the cyclic code to the feedback shift register
9
of the error detector
8
in the order in which they were demodulated.
FIG. 4
shows the respective states of the individual F/F circuits X
15
to X
0
when the feedback shift register
9
of the error detector
8
is operated. It is to be noted that
FIG. 4
shows the operation when the received cyclic code has no error.
In “STATE 0”, each of the F/F circuits X
15
to X
0
is reset to “0”. In “STATE 1” through “STATE 22”, the switch S
2
of
FIG. 2
is closed. The switch S
1
may be switched to either side.
The feedback shift register
9
sequentially receives the cyclic code “01 0101 0100 0010 0001 0100” from the input signal DIN
2
. In “STATE 22” in which the cyclic code has been received up to the least significant bit (hereinafter referred to as LSB) thereof, the values held by the F/F circuits X
15
to X
0
, i.e., t

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