Error detection system for a FIFO memory

Details Error detection system for a FIFO memory Error detection system for a FIFO memory

2005-08-30

2005-08-30

Baker, Stephen M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S824000

Reexamination Certificate

active

06938201

ABSTRACT:
An error detection system for detecting errors in data output from a FIFO memory includes a first CRC generator for receiving an inbound data stream and generating a first CRC value based on a data block in the inbound data stream. A device coupled to the first CRC generator selectively inputs the data block and the first CRC value into the FIFO. A second CRC generator generates a second CRC value based on the data block after being output from the FIFO in an outbound data stream. The second CRC value indicates whether the data block contains an error.

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Ross N. Williams; CRC Tutorial entitled “A Painless Guide to CRC Error Detection Algorithms”; Aug. 19, 1993; 29 pgs.
J.K. Weil and D. Chun, “The Single Burst Error Detection Performance of Binary Cyclic Codes”, IEEE Transactions on Communications, vol. 42, No. 1, Jan. 1994, pp. 11-13.
D. Chun and J.K. Weil, “Special Hardware for Computing the Probability of Undetected Error for Certain Binary CRC Codes and Test Results”, IEEE Transactions on Communications, vol. 42, No. 10, Oct. 1994, pp. 2769-2772.

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