Error detection in precharged logic

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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Reexamination Certificate

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08006147

ABSTRACT:
An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry have appropriate values. Error detection circuitry detects an error when the speculative node and the checker node are not one of both discharged or both undischarged.

REFERENCES:
patent: 5500688 (1996-03-01), Mok
patent: 6844762 (2005-01-01), Sanchez
patent: 7053663 (2006-05-01), Hazucha et al.
patent: 7546519 (2009-06-01), Agarwal
patent: 7705649 (2010-04-01), Yu et al.
patent: 2010/0244918 (2010-09-01), Moyer et al.
patent: 2010/0269018 (2010-10-01), Clark et al.

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