Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2011-03-22
2011-03-22
Alphonse, Fritz (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S718000, C714S807000
Reexamination Certificate
active
07913150
ABSTRACT:
An integrated circuit communications interface operable consistent with multiple data transmission protocols includes error detection circuitry that implements a cyclic redundancy check (i.e., CRC) function. The error detection circuitry generates a checksum based, at least in part, on a selected one of the multiple data transmission protocols. The error detection circuitry includes at least one circuit that generates a digital code according to an operation including terms common to the multiple data transmission protocols. That digital code is combined with a selected digital code to generate the CRC. The selected digital code is generated by an individual circuit corresponding to a respective one of the multiple data transmission protocols. The individual circuit generates the selected digital code according to an operation including at least terms exclusive to the respective one of the multiple data transmission protocols.
REFERENCES:
patent: 7031344 (2006-04-01), Rakib et al.
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patent: 7555016 (2009-06-01), Page
HyperTransportTM I/O Link Specification Revision 3.00, HyperTransport Technology Consortium, 428 pages, Apr. 21, 2006.
Wikipedia, “Error detection and correction,” 8 pp., retrieved Feb. 21, 2007 from URL:http://en.wikipedia.org/w/index.pho?title=Error—detection—and—correction&printable=yes.
Wikipedia, “Cyclic redundancy check,” 15 pp., retrieved Feb. 20, 2007 from URL://en.wikipedia.org/w/index.pho?title=Cyclic—redundancy—check&printable=yes.
Advanced Micro Devices , Inc.
Alphonse Fritz
Zagorin O'Brien Graham LLP
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