Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2010-09-09
2011-10-11
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S200000, C365S201000, C711S103000
Reexamination Certificate
active
08037381
ABSTRACT:
A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating to over-programmed bits in the primary array. When the over-programmed bits in the primary array are erased, the error documentation memory array is erased as well, deleting the documentation data relating to the over-programmed bits.
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patent: 6278632 (2001-08-01), Chevallier
patent: 6567302 (2003-05-01), Lakhani
patent: 6614689 (2003-09-01), Roohparvar
patent: 6614690 (2003-09-01), Roohparvar
patent: 7203874 (2007-04-01), Roohparvar
Gaffin Jeffrey A
Leffert Jay & Polglaze P.A.
McMahon Daniel F
Micro)n Technology, Inc.
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