Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2007-04-10
2007-04-10
Britt, Cynthia (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000, C711S103000
Reexamination Certificate
active
10431889
ABSTRACT:
A memory device has an error documentation memory array that is separate from the primary memory array. The error documentation memory array stores data relating to over-programmed bits in the primary array. When the over-programmed bits in the primary array are erased, the error documentation memory array is erased as well, deleting the documentation data relating to the over-programmed bits.
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patent: 5771346 (1998-06-01), Norman et al.
patent: 6577532 (2003-06-01), Chevallier
patent: 6614689 (2003-09-01), Roohparvar
patent: 6614690 (2003-09-01), Roohparvar
patent: 6907497 (2005-06-01), Hosono et al.
patent: 2003217288 (2002-01-01), None
Britt Cynthia
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
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