Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2011-01-11
2011-01-11
Chase, Shelly A (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
Reexamination Certificate
active
07870473
ABSTRACT:
An error detection device for an address decoder converting an input address to an associated output address out of a plurality of valid output addresses using a 1-out-of-n decoder, the error detection device including a regenerator for generating a regenerated address on the basis of the output address from the 1-out-of-n decoder, and a comparer for receiving the input address and the regenerated address and to output a signal, on the basis of a comparison of the input address and the regenerated address, which indicates an error in the conversion of the input address to the output address if the input address and the regenerated address do not match, and which indicates an error-free conversion of the input address to the output address if the input address equals the regenerated address.
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Ray, J et al.; “Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery”; Proceedings of the 34th annual ACM/IEEE International Symposium on Microarchitecture, Austin, Texas, 2001, pp. 214-224.
Goessel Michael
Guajardo Merchan Jorge
Klug Franz
Sonnekalb Steffen Marc
Chase Shelly A
Dickstein & Shapiro LLP
Infineon - Technologies AG
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