Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-02-08
2003-02-04
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
06516443
ABSTRACT:
FIELD OF INVENTION
The present invention relates to the recording and reproduction of binary data in disk storage systems for digital computers, particularly to a sampled amplitude read channel employing an error detection convolutional code and post processor for correcting the dominant error events of a trellis sequence detector.
BACKGROUND OF THE INVENTION
The advent and application of sophisticated digital signal processing techniques has increased dramatically the storage capacity of disk storage systems for digital computers by allowing for a significant increase in the linear storage density (number of bits stored per unit area along a concentric data track) without sacrificing performance in terms of the bit error rate. One particularly attractive digital signal processing technique previously applied in communication channels and more recently applied to the disk recording channel is Partial Response (PR) signaling with Maximum Likelihood (ML) sequence detection or PRML.
PR signaling refers to a particular method for transmitting symbols represented as analog pulses through a communication medium. The benefit is that at the signaling instances (baud rate) there is no intersymbol interference (ISI) from other pulses except for a controlled amount from immediately adjacent, overlapping pulses. Allowing the pulses to overlap in a controlled manner leads to an increase in the symbol rate (linear recording density) without losing performance in terms of signal-to-noise ratio (SNR).
PR channels are characterized by the polynomials
(1−
D
)(1+
D
)
n
where D represents a delay of one symbol period and n is an integer. For n=1,2,3, the PR channels are referred to as PR4, EPR4 and EEPR4, with their respective frequency responses shown in FIG.
1
A. The channel's dipulse response, the response to an isolated symbol, characterizes the transfer function of the system (the output for a given input). With a binary “1” bit modulating a positive dipulse response and a binary “0” bit modulating a negative dipulse response, the output of the channel is a linear combination of time shifted dipulse responses. The dipulse response for a PR4 channel (1−D
2
) is shown as a solid line in FIG.
1
B. Notice that at the symbol instances (baud rate), the dipulse response is zero except at times t=0 and t=2. Thus, the linear combination of time shifted PR4 dipulse responses will result in zero ISI at the symbol instances except where immediately adjacent pulses overlap.
With the PR4 dipulse samples normalized to (+1, 0 −1) it should be apparent that the linear combination of time shifted PR4 dipulse responses will result in a channel output of +2, 0, or −2 at the symbol instances depending on the binary input sequence. The output of the channel can therefore be characterized as a state machine driven by the binary input sequence, and conversely, the input sequence can be estimated or demodulated by running the signal samples at the output of the channel through an “inverse” state machine. Because noise will obfuscate the signal samples, the inverse state machine is actually implemented as a trellis sequence detector which computes a most likely input sequence associated with the signal samples (i.e., the sequence through a trellis that is closest to the signal samples in Euclidean space).
The performance of the trellis sequence detector in terms of bit error rate depends on the amount and character of noise in the system, including noise due to the spectrum of the read signal diverging from the ideal partial response. A channel equalizer is typically employed to shape the response of the read channel into the target partial response and to remove linear distortions in the read signal. The channel equalizer may be implemented in continous-time operating on the analog read signal, or it may be implemented in discrete-time operating on samples of the read signal, or both. Typical read channels employ an analog equalizer, such as a biquad analog filter, followed by a nth order finite-impulse response (FIR) discrete-time filter.
A drawback of the channel equalizers is that they tend to correlate the noise in the read signal, thereby degrading the performance of the trellis sequence detector which is a maximum likelihood detector only if the noise is additive white Gausian (AWG). Further, the undesirable noise correlating effect of the channel equalizers increases as the amount of equalization required to match the channel response to the target response increases. Increasing the order of the PR target generally decreases the amount of equalization required, but it also increases the cost and complexity of the trellis sequence detector due to the increase in the number of states in the trellis state machine. The amount of equalization required also increases as the linear bit density increases, which is inevitable given the perpetual increase in demand for higher capacity disk drives.
The aforementioned co-pending U.S. patent entitled “A SAMPLED AMPLITUDE READ CHANNEL EMPLOYING ITERATIVE ERROR CORRECTION TECHNIQUES TO MINIMIZE A EUCLIDEAN DISTANCE” ameliorates the degrading effect of the channel equalizers by providing a sample error filter which effectively whitens the noise in the read signal at the output of the channel equalizers. A post processor then evaluates the filtered sample errors (noise) to detect and correct errors made by the trellis sequence detector due to the noise correlating effect of the channel equalizers. In an alternative embodiment, an error detection channel code is also employed to further enhance the operation of the post processor by correcting only those errors detected by the error detection channel code, which reduces the probability of miscorrections. The particular error detection channel code disclosed in that application is a simple parity check bit over a predetermined number of channel data bits to form a parity error detection codeword. A simple parity code, however, is capable of detecting only a limited number of dominant error events associated with the trellis sequence detector. Error detection codes other than, or in addition to, a simple parity code could be employed to detect a greater number of the dominant error events, but an overall performance gain is realized only if the resulting code rate (channel bits to codeword bits) is high enough such that there is an increase in the user data density while still achieving some arbitrarily low bit error rate.
There is, therefore, a need for a sampled amplitude read channel for use in disk storage systems that improves the performance of a post processor by detecting and correcting a greater number of error events than that detectable using a simple parity code. An additional aspect of the present invention is to employ a high rate channel code capable of correcting several dominant error events of a trellis sequence detector, thereby allowing a significant increase in the user data density while still achieving some arbitrarily low bit error rate.
SUMMARY OF THE INVENTION
In a disk storage system for digital computers (e.g., optical or magnetic disk drives) a sampled amplitude read channel is disclosed comprising a convolutional code channel encoder for encoding check bits into channel data recorded to a disk storage medium, a trellis sequence detector for detecting a preliminary sequence from read signal sample values generated during read back, a convolutional code syndrome generator for generating an error syndrome from the preliminary sequence, and a post processor for evaluating the error syndrome to detect and correct errors made by the trellis sequence detector. The post processor remodulates the preliminary sequence output by the trellis sequence detector into a sequence of estimated sample values which are subtracted from the actual read signal sample values to form a sequence of sample errors. When the error syndrome indicates the presence of an error in the preliminary sequence, the post processor processes the sample errors to determine
Chase Shelly A
Cirrus Logic, Incorporated
De'cady Albert
Sheerin Howard
Shifrin Dan
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