Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
1999-09-09
2003-05-13
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C714S785000
Reexamination Certificate
active
06564352
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an error detection circuit applicable to an optical disk reproduction apparatus, such as a CD-ROM, and adapted to detect an error in a signal reproduced from an optical disk.
The recent trend is that optical disks are rotated at high speed, thereby reproducing data from the disks at high speed. Therefore, there is demand for an optical disk reproduction apparatus that can transfer data at a high rate. In general, data recorded on the optical disk, after being reproduced by a player, is transferred to a decode system through a signal processing circuit. The reproduced data is divided into data blocks called “sectors” and sent into a decode system.
Each sector data sent into the decode system contains, for example, a synchronizing signal SYNC representing a head of the block, HEADER and SUB HEADER having information on a position and mode form, USER DATA having user information, error detection code EDC, ECC parity of an error correction code, etc. These data contents differ from format mode to format mode. The format mode corresponds to data contents of one sector in a CD-ROM format mode of a MODE
2
FORM
1
.
For a decoder (for example, a CD-ROM decoder) in the decode system it is necessary to end the following functions (a) to (c) in a time inversely proportional to the reproduction speed of the disk.
(a) write transferred data into a buffer RAM.
(b) effect error detection and error correction of data.
(c) transfer data of a buffer RAM to a computer.
In order to improve the reproduction speed, therefore, it is necessary to have a very high access capability upon access to the buffer RAM.
In the decoder, error correction processing is made on per-sector data supplied from a player on the basis of a decided algorithm. This algorithm is of two types and either one of the following algorithms is adopted. The first algorithm is executed without any relation to the presence or absence of an error. The second algorithm performs error correction processing only when the error is detected.
In the case of adopting the first algorithm, with an improving reproduction speed of the disk, it is necessary that a capability of access to the buffer RAM, that is, the performance of error correction processing, be made very high. In order to effect error correction per sector, therefore, it is necessary to complete a series of access operations prior to transferring the next sector data.
The second algorithm decides the necessity for performing error correction processing through the utilization of an error detection code (EDC) initially containing the per-sector data supplied into the decode system and Interpolation Flag (IPF) (for example, a C
2
correction flag, C
2
correction failure flag or correction flag, etc.). If no error correction processing is required as a result of the decision, corresponding data is transferred to a host computer without performing the error correction processing.
The above-mentioned EDC contains data which is recorded on the disk as set out above. The IPF is added by an error correction system in a player upon signal processing. As a result, the EDC and IPF may be considered as an error detection means not necessary to gain access to the buffer RAM in the decode system. It is, therefore, not necessary for the error detection means to improve the performance of the buffer RAM and processing speed of the error correction circuit.
According to the decode system adopting the second algorithm, at least some of the data enables the omission of error correction processing. For this reason, data can be quickly transferred to the host computer. This can constitute a decode system having a high speed access time.
Incidentally, in the case where the reproduction speed of the disk is increased, more advantage is obtained in the adoption of the second algorithm with the user of the EDC and IPF for deciding whether or not to perform error correction processing than in the adoption of the first algorithm which encounters difficulties in improving the processing speed of the error correction circuit. That is, in the case of adopting the second algorithm, the transfer speed of the data is increased and it is not necessary to modify the buffer RAM and error correction circuit. This can prevent an increase in cost.
However, the EDC never takes part in making the error/correction of the data containing an ECC parity (Error Correction Code) added to correct an error in the per-sector data. This is because the ECC parity is not an object for error detection by the EDC.
Further, the IPF is information added under a player's own algorithm and never has any absolute reliability With an improving reproduction speed of the disk, the decision of the error correction necessity from only the EDC and IPF is not adequate to obtain high reliability upon reproduction of the disk.
BRIEF SUMMARY OF THE INVENTION
The present invention, solving the above disadvantages, provides an error detection circuit which can enhance an error detection capability in a decoder adopting an algorithm under which error correction processing is performed on per-sector data sent from a disk player into a decode system only when it is decided through an error detection that there is an error.
The objects of the present invention are achieved by the following devices.
According to one aspect of the present invention, an error detection circuit comprises an ECC error detection circuit supplied with data containing an ECC parity reproduced from a disk and calculating a syndrome for either of at least of P- and Q-correction with use of the data and ECC parity; and a latch circuit for retaining a calculation result.
According to another aspect of the present invention, a decode system comprises a decoder supplied with data containing an ECC parity reproduced from a disk; and a memory connected to the decoder and storing the data containing the ECC parity reproduced from the disk, wherein the decoder has an error detection circuit for calculating a syndrome for either of at least P- and Q-corrections as being supplied with the data containing the ECC parity.
According to another aspect of the present invention a decode system comprises a memory for storing data containing an EEC parity, error detection code (ECC) and interpolation flag (IPP) reproduced from the disk; a first error detection circuit for supplied with the data, the first error detection circuit calculating a syndrome for any of at least P- and Q-corrections with use of data containing the ECC parity; a second error detection circuit supplied with the data, the second error detection circuit detecting the EDC; and a third error detection circuit supplied with the data, the third error detection circuit detecting the IPF.
According to another aspect of the present invention, a decode system comprising: a decoder supplied with data containing an ECC parity reproduced from a disk; and a memory connected to the decoder and storing the data containing the ECC parity reproduced from the disk, the decoder having a calculation circuit for calculating a P correction syndrome and the calculation circuit being supplied with the data and calculating the P correction syndrome when the data is stored in the memory.
According to the present invention, in a decoder adopting an algorithm under which error correction processing is performed only when it is determined through an error correction that there is an error, the detection of the error is made, before the error correction processing, through the utilization of an ECC parity, whereby it is possible to remarkably improve the error detection capability.
According to the present invention, a P-correction syndrome is calculated simultaneously with the writing of data onto a buffer RAM and it is possible to perform the error correction and P-correction at high speeds. Even in the case where the reproduction of the disk is performed at high speeds, the data stored in the buffer RAM can be transferred to a host computer with an adequate allowance.
Additional obj
Furuhashi Shinobu
Sato Nobuhiro
Chung Phung M.
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
LandOfFree
Error detection circuit applicable to a disk reproduction... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Error detection circuit applicable to a disk reproduction..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Error detection circuit applicable to a disk reproduction... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3073628