Error detection and correction in data transmission packets

Details Error detection and correction in data transmission packets Error detection and correction in data transmission packets

2005-10-17

2008-11-04

Louis-Jacques, Jacques (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S784000, C714S756000

Reexamination Certificate

active

07447980

ABSTRACT:
A system and method of using recursive cyclic redundancy check (CRC)+forward error correction (FEC) for enhancing the channel coding gain for a DVB-H receiver, and using a physical (PHY) Reed-Solomon (RS) decoder+FEC to achieve better coding gain. The system and method utilize a dual mode RS decoder (erasure mode and error mode) for FEC decoding. The PHY RS is used to provide smaller granularity for FEC. The system includes a cache memory management scheme for implementing the recursive CRC/RS+FEC in very large scale integrated circuit chip (VLSI) hardware.

REFERENCES:
patent: 5956102 (1999-09-01), Lane
patent: 6044485 (2000-03-01), Dent et al.

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