Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-12-26
2006-12-26
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S781000, C714S758000, C714S746000, C714S800000, C714S752000, C714S762000, C375S340000, C360S053000, C370S216000
Reexamination Certificate
active
07155659
ABSTRACT:
A signal separation circuit (11) normally outputs a main signal, but outputs a TMCC signal when an error detection and correction unit (4) sets a completion flag. Main signals are input via a selection circuit (3) to an execution unit (4), where error correction of the main signals is performed. The error-corrected main signals are supplied via a switching circuit (8) to a first data output circuit (9). Meanwhile, TMCC signals are input via the selection circuit (3) to an execution unit (4), error correction is carried out to the TMCC signals. The error-corrected TMCC signals are supplied via switching circuit (8) to a second data output circuit (10).
REFERENCES:
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patent: 5383205 (1995-01-01), Makihara et al.
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patent: 6618450 (2003-09-01), Hatta
patent: 06-77844 (1994-03-01), None
Gandhi Dipakkumar
Lamarre Guy J.
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