Error detection and correction apparatus in a BY-4 RAM Device

Details Error detection and correction apparatus in a BY-4 RAM Device Error detection and correction apparatus in a BY-4 RAM Device

1991-11-22

1994-11-29

Beausoliel, Jr., Robert W.

Excavating

371 402, 371 372, H03M 1300

Patent

active

053696506

ABSTRACT:
A memory unit, made up of a plurality of BY-4 memory devices, has a plurality of computer words, each computer word including a predetermined number of data bits and a predetermined number of check bits. An error detection and correction (EDAC) apparatus interfaces with the memory unit for detecting and correcting a single bit error of the computer word, detecting a two bit error of the computer word, and detecting all two, three, and four bit errors of a single memory device. Matrix logic generates the check bits from preselected participating data bits of the data bits of the computer word being fetched. Compare gate logic compares check bits from the memory unit to corresponding check bits generated by the matrix logic to generate syndrome bits. Detection logic decodes the syndrome bits in accordance with a predetermined matrix mapped to identify one and two bit errors, to identify two, three, and four bit errors of the computer word when such errors are associated with the same BY-4 memory device, and to generate status signals associated with the decoding. Correction gate logic corrects the data bit of the computer word identified as being in error.

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Kaufman D., "Fault-Tolerant Memory with Single Error Correcting Codes", IBM Technical Disclosure Bulletin, vol. 26 No. 11, Apr. 1984, pp. 6142-6144.

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