Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-10-13
2002-08-13
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S786000, C714S794000, C714S795000, C375S262000, C375S341000
Reexamination Certificate
active
06434717
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device for detecting an error in a decoding result of an error correction code, for example, in a communications system or a broadcasting system, and a method thereof.
2. Description of the Related Art
In recent years, cellular phones have made remarkable progress and their market has rapidly been expanding. For such cellular phones, their communication devices must be reduced in size and consumption power, etc. A cellular phone of a smaller size, which is handy to carry, is considered to exploit a new market. Furthermore, if a cellular phone can support not only conventional voice communications but also data communications of, what is called, multimedia information such as documents, images, etc., its market value becomes very much large. Since such a cellular phone supporting data communications of multimedia information, etc. requires a large communication capacity as described above, it is vital to realize a large capacity communication with the smallest and simplest possible circuitry configuration. For this realization, it is inevitable to reduce an internal communication device in scale, weight, and size.
FIG. 1
is a block diagram showing the outline of the configuration of a conventional receiving device performing an error correction in reception data by using viterbi decoding which is one method of maximum likelihood decoding being one of error correction techniques in data communications, and CRC parity checking.
In this figure, remaining configuration except for the principal part relating to the present invention is omitted.
With viterbi decoding, data is decoded from its end. Therefore, also decoded data is output from its end to start. However, CRC checking cannot be made for viterbi-decoded data unchanged, which also affects data processing at subsequent stages. Therefore, after the bit order of viterbi-decoded data is inverted by storing the data output from a viterbi decoder
601
in a trace memory
603
and by reading the data from its start out of the trace memory
603
, CRC parity checking and reception data process are performed. The decoded data read from the trace memory
603
is transmitted to a CRC parity checking unit
604
, and also to a suitable processing circuit according to the type of the data. By way of example, after control data is converted from serial to parallel in a serial-to-parallel converter
605
, the parallel data is written to a reception buffer
606
. Upon completion of the write operation of the parallel data, a CPU
607
starts to read the data from the reception buffer
606
, and performs the corresponding process.
The band of a signal received from an antenna not shown is converted from an RF band to a baseband via an IF band. Then, the signal is deinterleaved by a deinterleaver
600
, and input to a viterbi decoder
601
. The viterbi decoder
601
is composed of a viterbi decoding circuit
602
and the trace memory
603
. As described above, the decoded data output from the viterbi decoding circuit
602
is output from its end to start in accordance with the decoding method. The trace memory
603
temporarily stores the data output from the viterbi decoding circuit
602
, and outputs the decoded data from its start to end under the control of a controlling unit not shown.
The decoded data output from the viterbi decoder
601
is input to the CRC parity checking unit
604
. The CRC parity checking unit
604
is a parity checking circuit which comprises a CRC circuit having the same configuration of that on a transmitting side. This unit generates a CRC bit for the decoded data with the CRC circuit, and determines whether or not the reception data includes an error by determining whether or not the generated CRC bit equals the CRC bit at the end of the decoded data. The determination result is notified from the CRC parity checking unit
604
to the CPU
607
or an adapter (ADP)
608
processing image data, etc.
The CPU
607
extracts the control data from the data stored in the reception buffer
606
, and performs control according to the contents of the control data. The data decoded by the viterbi decoder
601
is input also to the adapter
608
or a voice codec
609
. The adapter
608
or the voice codec
609
presents the input decoded data to a user as image or voice information via a facsimile
610
, a PC
611
, or a speaker
612
.
FIG. 2
shows the format of normal transmission data before convolutional encoding for viterbi decoding is not performed.
A CRC bit
616
is appended to the end of data to be transmitted (original data)
615
on a transmitting side as shown in this figure, and CRC checking is made on a receiving side, so that an error in the reception data can be detected. If an error is detected in the reception data, a receiving terminal performs processes such as a process for requesting a transmitting station to retransmit the same data.
FIG. 3
is a block diagram showing the configuration of a CRC circuit
619
arranged on a transmitting side.
The CRC circuit
619
shown in this figure comprises flip-flops
620
(D
1
) through
622
(D
3
), a selector
625
for controlling output data, and exclusive-OR operation units EXORs
623
and
624
.
Before the data
615
is input, all of the flip-flops
620
through
622
within the CRC (operation) circuit
619
are initialized (initiated to “0”). Then, the data
615
is input in bits, and a CRC operation is performed. The input data is captured into the CRC circuit
619
via the EXOR
624
. The CRC operation is performed for the entire input data, so that a CRC parity bit is generated. However, since the selector
625
selects a terminal “a” while the CRC operation is performed, output data becomes the same as the input data. The states of the flip-flops
620
through
622
when the data
615
is input to the end become the CRC parity bit
616
.
FIG. 3
shows the circuit for generating the CRC parity bit
616
composed of 3 bits. When the entire input data is output, the selector
625
selects a terminal “b”, and outputs the CRC parity bit
616
sequentially from D
3
(flip-flop
622
), D
2
(flip-flop
621
), to D
1
(flip-flop
620
). The output result
626
from the CRC circuit
616
is convolutional-encoded by a convolutional circuit which is not shown in this figure and arranged at the stage succeeding the CRC circuit, and is converted into a code which can be viterbi-decoded on a receiving side.
FIG. 4
shows the configuration of a CRC parity checking circuit
627
arranged in the device on a receiving side of the transmission data which is shown in FIG.
2
and is convolutional-encoded.
To make CRC parity checking on the receiving side, a CRC circuit
630
having the same configuration as that on a transmitting side is conventionally arranged. With this CRC circuit
630
, the CRC parity bit of the data corresponding to the original data
615
of the decoded data
629
obtained with viterbi decoding is operated. The result of the CRC operation when the data corresponding to the original data
615
of the decoded data
629
is input to the CRC circuit
630
to its end is temporarily stored in a CRC operation result storing unit
632
. Next, the CRC parity bit
616
appended on the transmitting side, that is, the CRC parity bit at the end of the decoded data
629
is extracted from the decoded data
629
, an is stored in a storing unit
633
. Then, the comparison between the bit value stored in the CRC operation result storing unit
632
and the bit value stored in the storing unit
633
is made. If they match, no error is determined to exist in the reception data. If they mismatch, an error is determined to exist in the reception data.
Conventionally, an error in reception data is detected by making CRC parity checking with the CRC circuit
630
having the same configuration as that of the CRC circuit
619
arranged in the device on a transmitting side as described above.
FIG. 5
explains the method for controlling a conventional reception buffer on a receiving side.
Fujitsu Limited
Katten Muchin Zavis & Rosenman
Moise Emmanuel L.
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