Error corrector

Details Error corrector Error corrector

1999-09-29

2003-04-01

Moise, Emmanuel L. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S758000, C714S777000, C714S805000

Reexamination Certificate

active

06543029

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates generally to data storage systems, and more particularly to data storage systems having redundancy arrangements to protect against total system failure in the event of a failure in a component or subassembly of the storage system.
As is known in the art, large mainframe computer systems require large capacity data storage systems. These large main frame computer systems generally include data processors which perform many operations on data introduced to the computer system through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system.
One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the main frame computer system are coupled together through an interface. The interface includes CPU, or “front end”, controllers (or directors) and “back end” disk controllers (or directors). The interface operates the controllers (or directors) in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the mainframe computer system merely thinks it is operating with one mainframe memory. One such system is described in U.S. Pat. No. 5,206,939, entitled “System and Method for Disk Mapping and Data Retrieval”, inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. Patent, the interface may also include, in addition to the CPU controllers (or directors) and disk controllers (or directors), addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the main frame computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the main frame computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The CPU controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk controllers are mounted on disk controller printed circuit boards. CPU controllers are mounted on CPU controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk controller, CPU controller and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a controller, the backplane printed circuit board has a pair of buses. One set the disk controllers is connected to one bus and another set of the disk controllers is connected to the other bus. Likewise, one set the CPU controllers is connected to one bus and another set of the CPU controllers is connected to the other bus. The cache memories are connected to both buses. Each one of the buses provides data, address and control information.
SUMMARY OF THE INVENTION
In accordance with the present invention, an error detector is provided. The error detector includes: a data source for providing data, such data having a plurality of bytes, each byte having a parity bit; a first logic for determining whether the parity bits have the same parity and for producing a combined parity bit representative of such determination; a check bit generator for producing a plurality of check bits from the data; a second logic for determining whether the produced check bits have the same logic state and for producing a combined check bit representative of such determination; a third logic to determine whether the combined check bit and the combined parity bit have the same logic state.
In accordance with another feature of the invention, a method is provided for checking errors in data. The method includes transmitting data along with parity bits to a first end of a data transmission network; generating check bits from the data as such data passes through the network; comparing the check bits with the parity bits to determine whether there has been an error generated by the network.
In one embodiment, the check bit generator produces the check bits in accordance with a redundancy check bit generating code. In one embodiment, the code is a Hamming code.
In accordance with another feature of the invention, an error detector is provided. The error detector includes a data source for providing data, such data having a plurality of bytes, each one of such bytes having a parity bit; a first XORing section for XORing the parity bits to reduce the parity bits to a combined parity bit; a check bit generator for producing a plurality of check bits from the data; a second XORing section for XORing the check bits to reduce the check bits to a combined check bit; a logic to determine whether the combined check bit and the combined parity bit have the same logic state.
In one embodiment, the check bit generator produces the check bits in accordance with a redundancy check bit generating code.
In one embodiment, the logic comprises XORing logic. The check bit generator produces the check bits in accordance with a redundancy check bit generating code.
In accordance with another feature of the invention, an error detector is provided. The detector includes: a data source for providing data; a check bit generator responsive to the data for generating check bits; a first logic for producing a combined parity bit from the generated check bit; a error detector/corrector adapted to detect an error in the data and adapted to correct such data in event of a detected error; a parity bit generator for producing a plurality parity bits from data produced by the error detector/corrector; a second logic for producing a combined parity bit representative of the produced plurality of parity bits; a third logic to determine whether the combined check bit and the combined parity bit have the same logic state.
In accordance with still another feature of the invention, an error detector is provided, comprising: a data source for providing data, such data having a plurality of bytes; a check bit generator for producing a plurality of check bits from the data; a first XORing section for XORing the check bits to reduce the check bits to a combined check bit; a error detector/corrector adapted to detect an error in the data and adapted to correct such data in event of a detected error; a parity bit generator for producing a plurality parity bits from data produced by the error detect or/corrector; a second XORing section for XORing the parity bits to reduce the parity bits to a combined parity bit; a third logic to determine whether the combined check bit and the combined parity bit have the same logic state.


REFERENCES:
patent: 4545077 (1985-10-01), Drapala et al.
patent: 5206939 (1993-04-01), Yanai et al.
patent: 5550804 (1996-08-01), Haussler et al.
patent: 5555250 (1996-09-01), Walker et al.
patent: 5638385 (1997-06-01), Fifield et al.
patent: 5721860 (1998-02-01), Stolt et al.
patent: 5734848 (1998-03-01), Gates et al.
patent: 5737745 (1998-04-01), Matsumoto et al.
patent: 5768530 (1998-06-01), Sandorfi
patent: 5829046 (1998-10-01), Tzelnic et al.
patent: 5954825 (1999-09-01), Kaiser et al.
patent: 6018778 (2000-01-01), Stolowitz
patent: 6112277 (2000-08-01), Bui et al.
patent: 6256705 (2001-07-01), Li et al.
patent: 6269424 (2001-07-01), Katsuragi et al.
patent: 6286083 (2001-09-01), Chin et al.
patent: 6304992 (2001-10-01), Cypher
patent: WO 00/39690 (2000-07-01), None
patent: WO 00/39691 (2000-07-01), None
Co-Pending patent application Ser. No. 09/408,058 filed Sep. 29, 1999 and Assigned to Art Unit 2818.
Co-Pending patent application Ser. No. 09/408,430 filed Sep. 29, 1999 and Assigned to Art Unit 2751.
Co-Pending patent application Ser. No. 09/408,807 filed Sep. 29, 1999 and Assigned to Art Unit 2751.
Co-Pending patent application Ser. No. 09/408,429 filed Sep. 29, 1999 and Assigned

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