Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-11-23
2001-07-31
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S746000
Reexamination Certificate
active
06269465
ABSTRACT:
BACKGROUND
The present invention relates to an error correction mechanism in a processing agent.
As is known, an agent may store data in an internal cache. Error correction codes permit a processing agent to identify corrupted data and determine whether the corrupted data can be corrected. Error correction techniques typically provide an error correction code associated with the data. When the data is stored, an error correction code, called a “syndrome,” is generated from the data and stored in association therewith. While the data is stored in the cache, it may suffer some type of data error. A second syndrome is generated from the data when it is retrieved from the cache. If the first syndrome and the second syndrome do not agree, a data error is identified. The syndromes may be used to identify and, possibly correct small errors. Typically, a one bit error in the data may be corrected based on the syndrome but a multi-bit error can not be corrected.
Error correction is a two-step process: error detection and data correction. In a first step, the locally generated syndrome is compared against the previously stored syndrome to detect errors. If an error is detected, a second step corrects the data where possible.
It is conventional to include error correction circuits in processing agents. Typically, error correction circuitry is included in an “outbound path” from the internal cache of an agent to its external bus. That is, when cached data is output from the agent, it passes through an error correction circuit as it propagates to an output of the agent. The error correction circuit corrects correctable errors present in the data.
Some agents also may include error correction circuits placed in an “inbound path” from the internal cache to, say, the agent's processing core. If used, the error correction circuit adds a predetermined amount of latency for every read of data from the internal cache to the core. Such an increase in latency is disfavored.
It is a goal of processing agents to process only non-corrupted data. Accordingly, error detection and correction must be performed on corrupted data before such data is processed by an agent.
It is also a goal of processing systems to retrieve and use data as quickly as possible. “Latency,” a time measured from the time a data request originates within an agent to the time that the data request is fulfilled, should be minimized. Error detection and correction circuitry increase data latency. If error correction and detection were performed every time data is retrieved from a cache, it would impose at least a two-cycle delay to every data retrieval operation: a first cycle would be consumed for error detection and a second cycle (or possibly several clock cycles) would be consumed for error correction. Adding latency to data retrieval operations for error detection and correction is disadvantageous because data corruption, although it significantly impairs processing performance when it is not detected, occurs relatively infrequently. Error detection and correction would impose a multi-cycle delay to every data transaction regardless of whether the transaction implicates corrupted data.
Accordingly, there is a need in the art for an error detection and correction mechanism in a processing agent that minimizes latency of data transactions that do not involve corrupted data but also prevents an agent from using corrupted data.
SUMMARY
Embodiments of the present invention provide an error correction method in an agent for stored data in which error detection is applied to requested data. When an error is detected, the requested data is output from the agent through an error correction circuit.
REFERENCES:
patent: 5146461 (1992-09-01), Duschatko et al.
patent: 5384788 (1995-01-01), Parks et al.
patent: 5477551 (1995-12-01), Parks et al.
patent: 5867510 (1999-02-01), Steele
Bachand Derek T.
Breuder Paul
Hill David L.
Prudvi Chinna
Chung Phung M.
Intel Corporation
Kenyon & Kenyon
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