Error correction scheme for memory

Details Error correction scheme for memory Error correction scheme for memory

2007-07-30

2009-12-22

Lamarre, Guy J (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S005110, C714S802000, C365S201000

Reexamination Certificate

active

07636880

ABSTRACT:
An embedded DRAM ECC architecture for purging data errors. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, and the parity block stores column parity bits. A row parity circuit coupled in parallel to an existing local databus of each memory checks the parity of the local databus bits against a row parity bit during a refresh or read operation to identify parity failure. Identification of the incorrect bit of the word is achieved by iteratively transferring the data of the local databus of each memory block onto an existing global databus, and checking the parity across the global databus with a column parity circuit. When global databus parity failure is detected, all bits of the global databus are inverted to purge the incorrect bit from the memory block via the local databus.

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