Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-05-18
2002-03-19
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S719000, C714S762000, C714S773000, C714S777000, C714S785000, C714S805000, C365S189050, C365S200000
Reexamination Certificate
active
06360347
ABSTRACT:
TECHNICAL FIELD
The present invention relates to error correction of data in a memory device, and more particularly, to an error correction method for a non-volatile memory device.
BACKGROUND ART
In semiconductor integrated memory devices, such as non-volatile memory devices, errors sometimes occur when data are written to or read from the memory devices. Sometimes errors in data storage may occur due to the physical characteristics of the memory devices. For example, in a conventional flash memory device, errors in the data stored in the flash memory may be caused by manufacturing defects or program disturbances. A program disturbance may be caused by an undesirable field turn-on in a typical conventional flash memory array during the programming of the memory gates in the conventional flash memory array. A field turn-on in the substrate region under the select gate transistor field oxide region between two memory gates on adjacent bit lines may cause one of the memory gates which is supposed to be in a program-inhibited state indicating a logic bit “1” to be “turned on” to a programmed state indicating a logic bit “0”. Bit errors in the data stored in a conventional non-volatile memory device may also be caused by various other factors.
In order to provide an acceptable level of reliability of data read from a conventional flash memory array, error correcting codes have been integrated into memory storage systems to correct bit errors in the data stored in the memory. Conventional error correcting codes such as block codes have been used in the error correction of data in conventional memory storage systems. For example, Hamming codes, which are within a class of conventional block codes well known to a person skilled in the art, have been used to provide single-bit error correction to preserve the accuracy of data in conventional memory storage devices.
Error checking and correction of data read from a flash memory array cause a delay from the time the data are pre-read from the memory by an error correction circuit to the time the error correction circuit enables the corrected data to be accessed externally by a host system. In order to minimize the time delay, error correction circuits have been implemented to compute the error addresses, that is, the syndrome generated by the error correcting block code, by parallel processing of the data read from the memory device. However, conventional error correction circuits with parallel processing capabilities can be very expensive to implement because of the complexity of the hardware. Parallel processing of data in the computation of the error addresses requires a large number of logic gates. For example, for every 1,000 bits of data read from the conventional flash memory device, approximately 5,000 XOR gates may be required for the parallel processing of data to minimize the delay in computing the syndrome.
Some applications may require that the cost of the memory storage system be minimized rather than the delay from the time of pre-reading the data from the memory array by the error correction circuit to the time the error correction circuit enables the corrected data to be read externally. In order to minimize the hardware cost, conventional error correction circuits and the methods have been implemented which involve serial processing of the data stored in the memory array to generate error addresses based upon a conventional error correcting block code. However, conventional serial processing may require hundreds of clock cycles of delay in the data access time before the data are read by the host system. A long time delay caused by the serial processing of the data may be unacceptable in some applications.
Therefore, there is a need for an error correction circuit and a method of error correction which are capable of reducing the cost of the hardware required for computing the error addresses compared to the hardware costs associated with the conventional parallel processing of the data read from the memory device, while reducing the data access time delay compared to the relatively long time delays resulting from the conventional serial processing of the data to generate the error addresses. Furthermore, there is a need for a method of allocating data words and error correction bytes in a page of memory to allow for efficient error correction while reducing the hardware cost.
DISCLOSURE OF THE INVENTION
The present invention satisfies these needs. In accordance with the present invention, a method of correcting an error in a memory device generally comprises the steps of:
(a) pre-reading a data word comprising a plurality of bytes identified by a plurality of data word byte addresses, comprising the step of counting the bytes of the data word to generate a plurality of byte ordinals for the bytes in the data word;
(b) coding the data word to generate a code word;
(c) generating a syndrome based upon the code word, the byte ordinals and the data word, the syndrome comprising a byte error address and a bit error address;
(d) comparing the data word byte address with the byte error address to determine whether the data word byte address matches the byte error address;
(e) generating an error correction enable signal in response to a determination by the step of comparing the data word byte address with the byte error address that the data word byte address matches the byte error address;
(f) decoding the bit error address to generate a decoded bit error address; and
(g) generating an error corrected byte based upon the decoded bit error address in response to the error correction enable signal.
In an embodiment in which each memory page comprises a plurality of data words including first and second data words, the error correction method further comprises the steps of pre-reading the second data word by an error correction circuit when the first data word is being read by the memory, and coding the second data word to generate a code word for the second data word when the first data word is being corrected and read.
In an embodiment, each memory page comprises three groups of data words. The first group comprises 10 data words each comprising 20 bytes. The second group comprises 13 data words each comprising 24 bytes. The last group comprises a single word having 16 bytes.
The steps of correcting errors in a data word as described above can be repeated for correcting errors, if any, in a plurality of data words within a page of memory. For error correction of data bytes in a memory array capable of storing a plurality of memory pages each comprising a plurality of data words, the method steps may be further repeated to correct errors, if any, in all of the data words within the memory pages. In an embodiment, each of the data words is coded by using a conventional error correcting block code, and in a further embodiment, the block code used for error correction comprises a conventional Hamming code.
In an embodiment, the syndrome generated by the error correcting code is an 8-bit syndrome byte which comprises a byte error address consisting of five bits and a bit error address consisting of three bits. The byte error address may be the higher order bits of the syndrome byte while the bit error address may be the lower order bits of the syndrome byte.
In an embodiment, the byte ordinals generated by the step of pre-reading the data word are represented in a binary format comprising a plurality of counter bits, at least two of the counter bits having a binary 1. In a further embodiment, the step of pre-reading the data word further comprises the step of rearranging the byte ordinals into a plurality of even bytes and a plurality of odd bytes. For example, for a data word which comprises a maximum of 26 data bytes, the renumbered byte ordinals for each of the data bytes within the data word may be represented as five counter bits, with at least two of the five counter bits having a binary 1. Furthermore, the byte ordinals may be renumbered and rearranged into odd bytes and even bytes, with the counter bits of the even bytes
Advanced Micro Devices , Inc.
Fliesler Dubb Meyer & Lovejoy LLP
Moise Emmanuel L.
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