Error correction method and apparatus thereof

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G06F 1110

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053156013

ABSTRACT:
An error correction method and apparatus for correcting multiple errors in received digital data word signals calculates syndromes S.sub.0, S.sub.1, S.sub.2 and S.sub.3 from a block of n received data words and a parity check matrix H. First coefficients .sigma..sub.1 and .sigma..sub.2 are calculated from the derived syndromes and a second coefficient K is calculated from the first coefficients .sigma..sub.1 and .sigma..sub.2. An error location value x.sub.1 is calculated from the second coefficient K, actual error location values X.sub.1 and X.sub.2 are calculated from the value x.sub.1, and error values Y.sub.1 and Y.sub.2 are calculated from the actual error location values X.sub.1 and X.sub.2. The received data words are then corrected by applying the calculated error values Y.sub.1 and Y.sub.2. The error location value x.sub.1 calculator is preferably constituted by logic gates which enable the apparatus to be smaller and faster than those using a conventional ROM table.

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patent: 4593394 (1986-06-01), Tomimitsu
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patent: 5068856 (1991-11-01), Nagasawa et al.
Transactions on Communications, vol. 39, No. 12, Dec. 8, 1991; `Closed solution of Berlekamp's algorithm for fast decoding of BCH codes`.

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