Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-04-17
2007-04-17
Kerveros, James C (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
11280892
ABSTRACT:
An integrated circuit, having a method therefor, includes a memory including a plurality of memory lines, each memory line including a plurality of data cells each to store a data bit, and a plurality of error-correction (EC) cells each to store an EC bit corresponding to the data bits stored in the data cells of the memory line; an EC input circuit to generate the EC bits based on the corresponding data bits; an EC output circuit including an EC correction circuit to correct errors in the bits read from the data cells of each of the memory lines in accordance with the bits read from the EC cells of the memory line; and a switch including first inputs to receive the EC bits from the EC input circuit, second inputs to receive test EC bits from EC test nodes of the integrated circuit, and outputs to provide either the EC bits or the EC test bits to the memory in accordance with a test signal.
REFERENCES:
patent: 4903268 (1990-02-01), Hidaka et al.
patent: 5056095 (1991-10-01), Horiguchi et al.
patent: 5127014 (1992-06-01), Raynham
patent: 5485595 (1996-01-01), Assar et al.
patent: 5535226 (1996-07-01), Drake et al.
patent: 5848076 (1998-12-01), Yoshimura
patent: 5958068 (1999-09-01), Arimilli et al.
patent: 5958079 (1999-09-01), Yoshimura
patent: 5959914 (1999-09-01), Gates et al.
patent: 5996107 (1999-11-01), Tomisawa
patent: 6000006 (1999-12-01), Bruce et al.
patent: 6058047 (2000-05-01), Kikuchi
patent: 6065141 (2000-05-01), Kitagawa
patent: 6175941 (2001-01-01), Poeppelman et al.
patent: 6237116 (2001-05-01), Fazel et al.
patent: 6295617 (2001-09-01), Sonobe
patent: 6385071 (2002-05-01), Chai et al.
patent: 6414876 (2002-07-01), Harari et al.
patent: 6438726 (2002-08-01), Walters, Jr.
patent: 6457154 (2002-09-01), Chen et al.
patent: 6938193 (2005-08-01), Honda
IBM Tech Disc. Bulletin NN85112562, “System for Efficiently Using Spare Memory Components for Defect Corrections Employing Content-Addressable Memory” Date: Nov. 1, 1985.
Schober et al., “Memory Built-in Self-repair Using Redundant Words” International Test Conference Proceedings, Publication Date: Oct. 30-Nov. 1, 2001 pp. 995-1001, Inspec Accession No.: 7211400.
Joshua Eitan
Solt Yosef
Kerveros James C
Marvell Semiconductor Israel Ltd.
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