Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-12-05
2010-12-28
Lamarre, Guy J (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07861138
ABSTRACT:
Embodiments of the invention generally provide a method and apparatus for correcting errors in a memory device. In one embodiment, the method includes receiving a read command and a read address for the read command and reading data from a first location of the memory device corresponding to the read address. The method also includes reading error correction information corresponding to the read address. If the error correction information indicates an error in the data, the error in the data is corrected to produce corrected data and the corrected data is output from the memory device. The corrected data is also written back to a second location in the memory device corresponding to the read address.
REFERENCES:
patent: 5937423 (1999-08-01), Robinson
patent: 6134681 (2000-10-01), Akamatsu et al.
patent: 2006/0059406 (2006-03-01), Micheloni et al.
NN8906375: Error Correction Codes With Address Checking; IBM Technical Disclosure Bulletin, vol. 32;Issue # 1,p. 375-377; Jun. 1, 1989.
Lamarre Guy J
Patterson & Sheridan LLP
Qimonda AG
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